diff options
| author | Thierry Reding | 2015-02-18 10:34:08 +0100 |
|---|---|---|
| committer | Thierry Reding | 2015-02-19 14:21:25 +0100 |
| commit | c03bf1bfd3a5448a4474f02b839f2195e3719cd9 (patch) | |
| tree | 5c26459346ad238abad0b20161b9f20899291449 /drivers/gpu | |
| parent | 45ee2dbc65cbf6910892c480e6f428be342fa733 (diff) | |
drm/tegra: hdmi: Explicitly set clock rate
Recent changes in the clock framework have caused a behavioural change
in that clocks that have not had their rate set explicitly will now be
reset to their initial rate (or 0) when the clock is released. This is
triggered in the deferred probing path, resulting in the clock running
at a wrong frequency after the successful probe.
This can be easily fixed by setting the rate explicitly rather than by
relying on the implicit rate inherited by the parent.
Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/tegra/hdmi.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 7e06657ae58b..7eaaee74a039 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -851,6 +851,14 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, h_back_porch = mode->htotal - mode->hsync_end; h_front_porch = mode->hsync_start - mode->hdisplay; + err = clk_set_rate(hdmi->clk, pclk); + if (err < 0) { + dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", + err); + } + + DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); + /* power up sequence */ value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); value &= ~SOR_PLL_PDBG; |