diff options
| author | Tao Zhang | 2024-02-04 13:30:33 +0800 |
|---|---|---|
| committer | Suzuki K Poulose | 2024-02-12 10:29:46 +0000 |
| commit | f021801c418e7a81455a410a5b195961349d8e93 (patch) | |
| tree | cacde664805e60c1e7768aeefef2351c8831e2a7 /drivers/hwtracing | |
| parent | 9f0ea8e8344b8549af404f2f1ddb25e22d6b09e1 (diff) | |
coresight-tpdm: Optimize the useage of tpdm_has_dsb_dataset
Since the function tpdm_has_dsb_dataset will be called by TPDA
driver in subsequent patches, it is moved to the header file.
And move this judgement form the function __tpdm_{enable/disable}
to the beginning of the function tpdm_{enable/disable}_dsb.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1707024641-22460-3-git-send-email-quic_taozha@quicinc.com
Diffstat (limited to 'drivers/hwtracing')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tpdm.c | 30 | ||||
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tpdm.h | 4 |
2 files changed, 18 insertions, 16 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 0427c0fc0bf3..4b1296d11360 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -125,11 +125,6 @@ static ssize_t tpdm_simple_dataset_store(struct device *dev, return ret; } -static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) -{ - return (drvdata->datasets & TPDM_PIDR0_DS_DSB); -} - static umode_t tpdm_dsb_is_visible(struct kobject *kobj, struct attribute *attr, int n) { @@ -232,25 +227,27 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) { u32 val, i; + if (!tpdm_has_dsb_dataset(drvdata)) + return; + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++) writel_relaxed(drvdata->dsb->edge_ctrl[i], - drvdata->base + TPDM_DSB_EDCR(i)); + drvdata->base + TPDM_DSB_EDCR(i)); for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++) writel_relaxed(drvdata->dsb->edge_ctrl_mask[i], - drvdata->base + TPDM_DSB_EDCMR(i)); + drvdata->base + TPDM_DSB_EDCMR(i)); for (i = 0; i < TPDM_DSB_MAX_PATT; i++) { writel_relaxed(drvdata->dsb->patt_val[i], - drvdata->base + TPDM_DSB_TPR(i)); + drvdata->base + TPDM_DSB_TPR(i)); writel_relaxed(drvdata->dsb->patt_mask[i], - drvdata->base + TPDM_DSB_TPMR(i)); + drvdata->base + TPDM_DSB_TPMR(i)); writel_relaxed(drvdata->dsb->trig_patt[i], - drvdata->base + TPDM_DSB_XPR(i)); + drvdata->base + TPDM_DSB_XPR(i)); writel_relaxed(drvdata->dsb->trig_patt_mask[i], - drvdata->base + TPDM_DSB_XPMR(i)); + drvdata->base + TPDM_DSB_XPMR(i)); } set_dsb_tier(drvdata); - set_dsb_msr(drvdata); val = readl_relaxed(drvdata->base + TPDM_DSB_CR); @@ -278,8 +275,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - if (tpdm_has_dsb_dataset(drvdata)) - tpdm_enable_dsb(drvdata); + tpdm_enable_dsb(drvdata); CS_LOCK(drvdata->base); } @@ -307,6 +303,9 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) { u32 val; + if (!tpdm_has_dsb_dataset(drvdata)) + return; + /* Set the enable bit of DSB control register to 0 */ val = readl_relaxed(drvdata->base + TPDM_DSB_CR); val &= ~TPDM_DSB_CR_ENA; @@ -318,8 +317,7 @@ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); - if (tpdm_has_dsb_dataset(drvdata)) - tpdm_disable_dsb(drvdata); + tpdm_disable_dsb(drvdata); CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h index 4115b2a17b8d..ddaf333fa1c2 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.h +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -220,4 +220,8 @@ struct tpdm_dataset_attribute { u32 idx; }; +static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata) +{ + return (drvdata->datasets & TPDM_PIDR0_DS_DSB); +} #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ |