diff options
| author | Ben Collins | 2006-06-12 18:13:32 -0400 |
|---|---|---|
| committer | Ben Collins | 2006-06-12 18:13:32 -0400 |
| commit | 4611ed38030a2ce3661de999c3487e5a1eed0dc0 (patch) | |
| tree | bd0924844e1b5b5ccefc4ee5cf81c917b8781e5c /drivers/ieee1394 | |
| parent | 8aef63ff033fb0e7ba02d8e760d268eb0aafc58c (diff) | |
ohci1394: set address range properties
This patch supplies the API extension introduced by patch
"ieee1394: extend lowlevel API for address range properties"
with proper addresses.
Like in patch ''ohci1394, sbp2: fix "scsi_add_device failed"
with PL-3507 based devices'', 1 TeraByte is chosen as physical
upper bound. This leaves a window for the middle address range.
This choice is only relevant for adapters which actually have a
programmable pysical upper bound register. (Only ALi and
Fujitsu adapters are known for this. Most adapters have a fixed
bound at 4 GB.) The middle address range is suitable for posted
writes.
AFAIK, PCILynx does not support physical DMA nor posted writes,
therefore no equivalent change in the pcilynx driver is necessary.
There is also a driver for GP2Lynx, although not in mainline Linux.
I assume this hardware does not support these OHCI features either.
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
Signed-off-by: Ben Collins <bcollins@ubuntu.com>
Diffstat (limited to 'drivers/ieee1394')
| -rw-r--r-- | drivers/ieee1394/ohci1394.c | 11 | ||||
| -rw-r--r-- | drivers/ieee1394/ohci1394.h | 10 |
2 files changed, 20 insertions, 1 deletions
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c index 643094c3339c..63b71fa997fc 100644 --- a/drivers/ieee1394/ohci1394.c +++ b/drivers/ieee1394/ohci1394.c @@ -553,7 +553,8 @@ static void ohci_initialize(struct ti_ohci *ohci) * register content. * To actually enable physical responses is the job of our interrupt * handler which programs the physical request filter. */ - reg_write(ohci, OHCI1394_PhyUpperBound, 0x01000000); + reg_write(ohci, OHCI1394_PhyUpperBound, + OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16); DBGMSG("physUpperBoundOffset=%08x", reg_read(ohci, OHCI1394_PhyUpperBound)); @@ -3414,6 +3415,14 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev, host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf; host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7; + if (phys_dma) { + host->low_addr_space = + (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16; + if (!host->low_addr_space) + host->low_addr_space = OHCI1394_PHYS_UPPER_BOUND_FIXED; + } + host->middle_addr_space = OHCI1394_MIDDLE_ADDRESS_SPACE; + /* Tell the highlevel this host is ready */ if (hpsb_add_host(host)) FAIL(-ENOMEM, "Failed to register host with highlevel"); diff --git a/drivers/ieee1394/ohci1394.h b/drivers/ieee1394/ohci1394.h index 7df0962144e3..fa05f113f7f0 100644 --- a/drivers/ieee1394/ohci1394.h +++ b/drivers/ieee1394/ohci1394.h @@ -443,6 +443,16 @@ static inline u32 reg_read(const struct ti_ohci *ohci, int offset) #define OHCI1394_TCODE_PHY 0xE +/* Node offset map (phys DMA area, posted write area). + * The value of OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED may be modified but must + * be lower than OHCI1394_MIDDLE_ADDRESS_SPACE. + * OHCI1394_PHYS_UPPER_BOUND_FIXED and OHCI1394_MIDDLE_ADDRESS_SPACE are + * constants given by the OHCI spec. + */ +#define OHCI1394_PHYS_UPPER_BOUND_FIXED 0x000100000000ULL /* 4 GB */ +#define OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED 0x010000000000ULL /* 1 TB */ +#define OHCI1394_MIDDLE_ADDRESS_SPACE 0xffff00000000ULL + void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, int type, void (*func)(unsigned long), |