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authorJonathan Cameron2022-05-08 18:56:40 +0100
committerJonathan Cameron2022-06-14 11:53:17 +0100
commite66bf04797f1f95a2402414c00e64d00f63d31ec (patch)
tree11c897d58486fa7b88957767adb73753d6a0188f /drivers/iio/dac
parent2030708377a219b548a9a36da57d3852382baf1d (diff)
iio: dac: mcp4922: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Fixes: 1b791fadf3a1 ("iio: dac: mcp4902/mcp4912/mcp4922 dac driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Michael Welling <mwelling@ieee.org> Link: https://lore.kernel.org/r/20220508175712.647246-61-jic23@kernel.org
Diffstat (limited to 'drivers/iio/dac')
-rw-r--r--drivers/iio/dac/mcp4922.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/dac/mcp4922.c b/drivers/iio/dac/mcp4922.c
index cb9e60e71b91..6c0e31032c57 100644
--- a/drivers/iio/dac/mcp4922.c
+++ b/drivers/iio/dac/mcp4922.c
@@ -29,7 +29,7 @@ struct mcp4922_state {
unsigned int value[MCP4922_NUM_CHANNELS];
unsigned int vref_mv;
struct regulator *vref_reg;
- u8 mosi[2] ____cacheline_aligned;
+ u8 mosi[2] __aligned(IIO_DMA_MINALIGN);
};
#define MCP4922_CHAN(chan, bits) { \