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authorLinus Torvalds2022-03-23 18:03:08 -0700
committerLinus Torvalds2022-03-23 18:03:08 -0700
commit194dfe88d62ed12d0cf30f6f20734c2d0d111533 (patch)
treef057597d411df53a152ac41ae8bd900aabb94994 /drivers/irqchip
parent9c0e6a89b592f4c4e4d769dbc22d399ab0685159 (diff)
parentaec499c75cf8e0b599be4d559e6922b613085f8f (diff)
Merge tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic updates from Arnd Bergmann: "There are three sets of updates for 5.18 in the asm-generic tree: - The set_fs()/get_fs() infrastructure gets removed for good. This was already gone from all major architectures, but now we can finally remove it everywhere, which loses some particularly tricky and error-prone code. There is a small merge conflict against a parisc cleanup, the solution is to use their new version. - The nds32 architecture ends its tenure in the Linux kernel. The hardware is still used and the code is in reasonable shape, but the mainline port is not actively maintained any more, as all remaining users are thought to run vendor kernels that would never be updated to a future release. - A series from Masahiro Yamada cleans up some of the uapi header files to pass the compile-time checks" * tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (27 commits) nds32: Remove the architecture uaccess: remove CONFIG_SET_FS ia64: remove CONFIG_SET_FS support sh: remove CONFIG_SET_FS support sparc64: remove CONFIG_SET_FS support lib/test_lockup: fix kernel pointer check for separate address spaces uaccess: generalize access_ok() uaccess: fix type mismatch warnings from access_ok() arm64: simplify access_ok() m68k: fix access_ok for coldfire MIPS: use simpler access_ok() MIPS: Handle address errors for accesses above CPU max virtual user address uaccess: add generic __{get,put}_kernel_nofault nios2: drop access_ok() check from __put_user() x86: use more conventional access_ok() definition x86: remove __range_not_ok() sparc64: add __{get,put}_kernel_nofault() nds32: fix access_ok() checks in get/put_user uaccess: fix nios2 and microblaze get_user_8() sparc64: fix building assembly files ...
Diffstat (limited to 'drivers/irqchip')
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/irq-ativic32.c156
2 files changed, 0 insertions, 157 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 1f8990f812f1..160a1d8ceaa9 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -92,7 +92,6 @@ obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o
obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o
-obj-$(CONFIG_NDS32) += irq-ativic32.o
obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o
obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o
obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o
diff --git a/drivers/irqchip/irq-ativic32.c b/drivers/irqchip/irq-ativic32.c
deleted file mode 100644
index 223dd2f97d28..000000000000
--- a/drivers/irqchip/irq-ativic32.c
+++ /dev/null
@@ -1,156 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-// Copyright (C) 2005-2017 Andes Technology Corporation
-
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/hardirq.h>
-#include <linux/interrupt.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip.h>
-#include <nds32_intrinsic.h>
-
-#include <asm/irq_regs.h>
-
-unsigned long wake_mask;
-
-static void ativic32_ack_irq(struct irq_data *data)
-{
- __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2);
-}
-
-static void ativic32_mask_irq(struct irq_data *data)
-{
- unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
- __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2);
-}
-
-static void ativic32_unmask_irq(struct irq_data *data)
-{
- unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2);
- __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2);
-}
-
-static int nointc_set_wake(struct irq_data *data, unsigned int on)
-{
- unsigned long int_mask = __nds32__mfsr(NDS32_SR_INT_MASK);
- static unsigned long irq_orig_bit;
- u32 bit = 1 << data->hwirq;
-
- if (on) {
- if (int_mask & bit)
- __assign_bit(data->hwirq, &irq_orig_bit, true);
- else
- __assign_bit(data->hwirq, &irq_orig_bit, false);
-
- __assign_bit(data->hwirq, &int_mask, true);
- __assign_bit(data->hwirq, &wake_mask, true);
-
- } else {
- if (!(irq_orig_bit & bit))
- __assign_bit(data->hwirq, &int_mask, false);
-
- __assign_bit(data->hwirq, &wake_mask, false);
- __assign_bit(data->hwirq, &irq_orig_bit, false);
- }
-
- __nds32__mtsr_dsb(int_mask, NDS32_SR_INT_MASK);
-
- return 0;
-}
-
-static struct irq_chip ativic32_chip = {
- .name = "ativic32",
- .irq_ack = ativic32_ack_irq,
- .irq_mask = ativic32_mask_irq,
- .irq_unmask = ativic32_unmask_irq,
- .irq_set_wake = nointc_set_wake,
-};
-
-static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 };
-
-static struct irq_domain *root_domain;
-static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq,
- irq_hw_number_t hw)
-{
-
- unsigned long int_trigger_type;
- u32 type;
- struct irq_data *irq_data;
- int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER);
- irq_data = irq_get_irq_data(virq);
- if (!irq_data)
- return -EINVAL;
-
- if (int_trigger_type & (BIT(hw))) {
- irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq);
- type = IRQ_TYPE_EDGE_RISING;
- } else {
- irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq);
- type = IRQ_TYPE_LEVEL_HIGH;
- }
-
- irqd_set_trigger_type(irq_data, type);
- return 0;
-}
-
-static const struct irq_domain_ops ativic32_ops = {
- .map = ativic32_irq_domain_map,
- .xlate = irq_domain_xlate_onecell
-};
-
-static irq_hw_number_t get_intr_src(void)
-{
- return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> ITYPE_offVECTOR)
- - NDS32_VECTOR_offINTERRUPT;
-}
-
-static void ativic32_handle_irq(struct pt_regs *regs)
-{
- irq_hw_number_t hwirq = get_intr_src();
- generic_handle_domain_irq(root_domain, hwirq);
-}
-
-/*
- * TODO: convert nds32 to GENERIC_IRQ_MULTI_HANDLER so that this entry logic
- * can live in arch code.
- */
-asmlinkage void asm_do_IRQ(struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
-
- irq_enter();
- old_regs = set_irq_regs(regs);
- ativic32_handle_irq(regs);
- set_irq_regs(old_regs);
- irq_exit();
-}
-
-int __init ativic32_init_irq(struct device_node *node, struct device_node *parent)
-{
- unsigned long int_vec_base, nivic, nr_ints;
-
- if (WARN(parent, "non-root ativic32 are not supported"))
- return -EINVAL;
-
- int_vec_base = __nds32__mfsr(NDS32_SR_IVB);
-
- if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0)
- panic("Unable to use atcivic32 for this cpu.\n");
-
- nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC;
- if (nivic >= ARRAY_SIZE(nivic_map))
- panic("The number of input for ativic32 is not supported.\n");
-
- nr_ints = nivic_map[nivic];
-
- root_domain = irq_domain_add_linear(node, nr_ints,
- &ativic32_ops, NULL);
-
- if (!root_domain)
- panic("%s: unable to create IRQ domain\n", node->full_name);
-
- return 0;
-}
-IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq);