diff options
| author | Samuel Holland | 2024-03-12 14:28:08 -0700 |
|---|---|---|
| committer | Thomas Gleixner | 2024-03-15 15:27:02 +0100 |
| commit | ca5b0b717b75d0f86f7f5dfe18369781bec742ad (patch) | |
| tree | d1f8f912e858b9dd50353b8e9227553a3ee3ddf1 /drivers/irqchip | |
| parent | 4527e837801e76bbb196bb3b19375d8e43d636be (diff) | |
irqchip/riscv-intc: Fix use of AIA interrupts 32-63 on riscv32
riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second
check passes even though AIA provides 64 interrupts. Adjust the condition to
only check the custom range for interrupts outside the standard range, and
adjust the standard range when AIA is available.
Fixes: 3c46fc5b5507 ("irqchip/riscv-intc: Add support for RISC-V AIA")
Fixes: 678c607ecf8a ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20240312212813.2323841-1-samuel.holland@sifive.com
Diffstat (limited to 'drivers/irqchip')
| -rw-r--r-- | drivers/irqchip/irq-riscv-intc.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f87aeab460eb..9e71c4428814 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -149,8 +149,9 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain, * Only allow hwirq for which we have corresponding standard or * custom interrupt enable register. */ - if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) || - (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs)) + if (hwirq >= riscv_intc_nr_irqs && + (hwirq < riscv_intc_custom_base || + hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs)) return -EINVAL; for (i = 0; i < nr_irqs; i++) { @@ -183,10 +184,12 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch return -ENXIO; } - if (riscv_isa_extension_available(NULL, SxAIA)) + if (riscv_isa_extension_available(NULL, SxAIA)) { + riscv_intc_nr_irqs = 64; rc = set_handle_irq(&riscv_intc_aia_irq); - else + } else { rc = set_handle_irq(&riscv_intc_irq); + } if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -195,7 +198,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch riscv_set_intc_hwnode_fn(riscv_intc_hwnode); pr_info("%d local interrupts mapped%s\n", - riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs, + riscv_intc_nr_irqs, riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : ""); if (riscv_intc_custom_nr_irqs) pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs); |