diff options
| author | Kai-Heng Feng | 2022-04-07 20:12:28 +0800 |
|---|---|---|
| committer | Alex Deucher | 2022-04-13 22:21:58 -0400 |
| commit | 887f75cfd0da44c19dda93b2ff9e70ca8792cdc1 (patch) | |
| tree | bcbec20a3ccc8992c3066aae17379fab40d0beac /drivers/mfd/intel_soc_pmic_bxtwc.c | |
| parent | e3cf2e05441a2c5107fbffadb5b7943113ee11dd (diff) | |
drm/amdgpu: Ensure HDA function is suspended before ASIC reset
DP/HDMI audio on AMD PRO VII stops working after S3:
[ 149.450391] amdgpu 0000:63:00.0: amdgpu: MODE1 reset
[ 149.450395] amdgpu 0000:63:00.0: amdgpu: GPU mode1 reset
[ 149.450494] amdgpu 0000:63:00.0: amdgpu: GPU psp mode1 reset
[ 149.983693] snd_hda_intel 0000:63:00.1: refused to change power state from D0 to D3hot
[ 150.003439] amdgpu 0000:63:00.0: refused to change power state from D0 to D3hot
...
[ 155.432975] snd_hda_intel 0000:63:00.1: CORB reset timeout#2, CORBRP = 65535
The offending commit is daf8de0874ab5b ("drm/amdgpu: always reset the asic in
suspend (v2)"). Commit 34452ac3038a7 ("drm/amdgpu: don't use BACO for
reset in S3 ") doesn't help, so the issue is something different.
Assuming that to make HDA resume to D0 fully realized, it needs to be
successfully put to D3 first. And this guesswork proves working, by
moving amdgpu_asic_reset() to noirq callback, so it's called after HDA
function is in D3.
Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)")
Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/mfd/intel_soc_pmic_bxtwc.c')
0 files changed, 0 insertions, 0 deletions