diff options
author | Dominik Brodowski | 2010-07-24 12:23:21 +0200 |
---|---|---|
committer | Dominik Brodowski | 2010-08-03 09:02:35 +0200 |
commit | 1d5cc192d431bce2ebe9fde64054ce903200e179 (patch) | |
tree | cdcdfb77712349bf46f0876d420e2be81f901d74 /drivers/net/pcmcia | |
parent | ac8b422838046ffc26be4874a3cbae0d313f4209 (diff) |
pcmcia: use pcmica_{read,write}_config_byte
Use pcmcia_read_config_byte and pcmcia_write_config_byte instead
of pcmcia_access_configuration_register.
CC: netdev@vger.kernel.org
CC: linux-wireless@vger.kernel.org
CC: linux-serial@vger.kernel.org
CC: Michael Buesch <mb@bu3sch.de>
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Diffstat (limited to 'drivers/net/pcmcia')
-rw-r--r-- | drivers/net/pcmcia/axnet_cs.c | 3 | ||||
-rw-r--r-- | drivers/net/pcmcia/nmclan_cs.c | 21 | ||||
-rw-r--r-- | drivers/net/pcmcia/xirc2ps_cs.c | 16 |
3 files changed, 14 insertions, 26 deletions
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c index 467fd4bfb2bd..ee0a6d036f94 100644 --- a/drivers/net/pcmcia/axnet_cs.c +++ b/drivers/net/pcmcia/axnet_cs.c @@ -378,8 +378,7 @@ static int axnet_config(struct pcmcia_device *link) /* Maybe PHY is in power down mode. (PPD_SET = 1) Bit 2 of CCSR is active low. */ if (i == 32) { - conf_reg_t reg = { 0, CS_WRITE, CISREG_CCSR, 0x04 }; - pcmcia_access_configuration_register(link, ®); + pcmcia_write_config_byte(link, CISREG_CCSR, 0x04); for (i = 0; i < 32; i++) { j = mdio_read(dev->base_addr + AXNET_MII_EEP, i, 1); j2 = mdio_read(dev->base_addr + AXNET_MII_EEP, i, 2); diff --git a/drivers/net/pcmcia/nmclan_cs.c b/drivers/net/pcmcia/nmclan_cs.c index c0eacfae1512..c0d85af3e942 100644 --- a/drivers/net/pcmcia/nmclan_cs.c +++ b/drivers/net/pcmcia/nmclan_cs.c @@ -757,29 +757,20 @@ static void nmclan_reset(struct net_device *dev) #if RESET_XILINX struct pcmcia_device *link = &lp->link; - conf_reg_t reg; - u_long OrigCorValue; + u8 OrigCorValue; /* Save original COR value */ - reg.Function = 0; - reg.Action = CS_READ; - reg.Offset = CISREG_COR; - reg.Value = 0; - pcmcia_access_configuration_register(link, ®); - OrigCorValue = reg.Value; + pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); /* Reset Xilinx */ - reg.Action = CS_WRITE; - reg.Offset = CISREG_COR; - dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n", + dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n", OrigCorValue); - reg.Value = COR_SOFT_RESET; - pcmcia_access_configuration_register(link, ®); + pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); /* Need to wait for 20 ms for PCMCIA to finish reset. */ /* Restore original COR configuration index */ - reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK); - pcmcia_access_configuration_register(link, ®); + pcmcia_write_config_byte(link, CISREG_COR, + (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); /* Xilinx is now completely reset along with the MACE chip. */ lp->tx_free_frames=AM2150_MAX_TX_FRAMES; diff --git a/drivers/net/pcmcia/xirc2ps_cs.c b/drivers/net/pcmcia/xirc2ps_cs.c index a7662f0832eb..e3a85ce89880 100644 --- a/drivers/net/pcmcia/xirc2ps_cs.c +++ b/drivers/net/pcmcia/xirc2ps_cs.c @@ -869,7 +869,6 @@ xirc2ps_config(struct pcmcia_device * link) goto config_error; if (local->dingo) { - conf_reg_t reg; win_req_t req; memreq_t mem; @@ -878,15 +877,14 @@ xirc2ps_config(struct pcmcia_device * link) * the base address of the ethernet port (BasePort1) is written * to the BAR registers of the modem. */ - reg.Action = CS_WRITE; - reg.Offset = CISREG_IOBASE_0; - reg.Value = link->io.BasePort2 & 0xff; - if ((err = pcmcia_access_configuration_register(link, ®))) + err = pcmcia_write_config_byte(link, CISREG_IOBASE_0, + link->io.BasePort2 & 0xff); + if (err) goto config_error; - reg.Action = CS_WRITE; - reg.Offset = CISREG_IOBASE_1; - reg.Value = (link->io.BasePort2 >> 8) & 0xff; - if ((err = pcmcia_access_configuration_register(link, ®))) + + err = pcmcia_write_config_byte(link, CISREG_IOBASE_1, + (link->io.BasePort2 >> 8) & 0xff); + if (err) goto config_error; /* There is no config entry for the Ethernet part which |