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authorHeiner Kallweit2020-04-23 21:38:42 +0200
committerDavid S. Miller2020-04-24 16:47:51 -0700
commit9576e9fa1c02aea3cf1e42eadcbeb12ccf5e87de (patch)
treef4d442689a28a1719e0e5a1323679472127df000 /drivers/net/phy/phy_device.c
parent3194915486b2bc3f77745774f1731b78f32ff688 (diff)
net: phy: clear phydev->suspended after soft reset
If a soft reset is triggered whilst PHY is in power-down, then phydev->suspended will remain set. Seems we didn't face any issue yet caused by this, but better reset the suspended flag after soft reset. See also the following from 22.2.4.1.1 Resetting a PHY is accomplished by setting bit 0.15 to a logic one. This action shall set the status and control registers to their default states. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/phy_device.c')
-rw-r--r--drivers/net/phy/phy_device.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index c8f8fd9908fe..7e1ddd5745d2 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1082,8 +1082,12 @@ int phy_init_hw(struct phy_device *phydev)
if (!phydev->drv)
return 0;
- if (phydev->drv->soft_reset)
+ if (phydev->drv->soft_reset) {
ret = phydev->drv->soft_reset(phydev);
+ /* see comment in genphy_soft_reset for an explanation */
+ if (!ret)
+ phydev->suspended = 0;
+ }
if (ret < 0)
return ret;
@@ -2157,6 +2161,12 @@ int genphy_soft_reset(struct phy_device *phydev)
if (ret < 0)
return ret;
+ /* Clause 22 states that setting bit BMCR_RESET sets control registers
+ * to their default value. Therefore the POWER DOWN bit is supposed to
+ * be cleared after soft reset.
+ */
+ phydev->suspended = 0;
+
ret = phy_poll_reset(phydev);
if (ret)
return ret;