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authorBenoit PAPILLAULT2009-10-22 12:04:52 +0200
committerJohn W. Linville2009-10-27 16:48:35 -0400
commit7f4013f09654216653121f216bd0257f460f5dcc (patch)
treeb60eaaa057005c614f65f07aac6f65628c35f6b0 /drivers/net/wireless/zd1211rw/zd_chip.h
parent287d37412035d003430f69a828c98b1cc6ee6d60 (diff)
zd1211rw: Fix TX status reporting in order to have proper rate control
First, we reduce the number of hardware retries to 0 (ie 2 real retries for each rate). Next, when we report the retries to mac80211, we always report a retry count of 1 (it seems to be 2 in fact, but using 2 seems to lead to wrong performance for some reason). We use a state machine to determine the real fate of a packet based on the 802.11 ACK and what the Zydas hardware is saying when a real retry occurs. The real retry rates are encoded in a static array. It has been tested with both zd1211 and zd1211b hardware. Of course, since the Zydas hardware is not reporting retries accurately, we are just doing our best in order to get the best performance (ie higher throughput). Signed-off-by: Benoit PAPILLAULT <benoit.papillault@free.fr> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/zd1211rw/zd_chip.h')
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.h18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h
index 678c139a840c..9fd8f3508d66 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.h
+++ b/drivers/net/wireless/zd1211rw/zd_chip.h
@@ -642,13 +642,29 @@ enum {
#define CR_ZD1211B_TXOP CTL_REG(0x0b20)
#define CR_ZD1211B_RETRY_MAX CTL_REG(0x0b28)
+/* Value for CR_ZD1211_RETRY_MAX & CR_ZD1211B_RETRY_MAX. Vendor driver uses 2,
+ * we use 0. The first rate is tried (count+2), then all next rates are tried
+ * twice, until 1 Mbits is tried. */
+#define ZD1211_RETRY_COUNT 0
+#define ZD1211B_RETRY_COUNT \
+ (ZD1211_RETRY_COUNT << 0)| \
+ (ZD1211_RETRY_COUNT << 8)| \
+ (ZD1211_RETRY_COUNT << 16)| \
+ (ZD1211_RETRY_COUNT << 24)
+
/* Used to detect PLL lock */
#define UW2453_INTR_REG ((zd_addr_t)0x85c1)
#define CWIN_SIZE 0x007f043f
-#define HWINT_ENABLED 0x004f0000
+#define HWINT_ENABLED \
+ (INT_TX_COMPLETE_EN| \
+ INT_RX_COMPLETE_EN| \
+ INT_RETRY_FAIL_EN| \
+ INT_WAKEUP_EN| \
+ INT_CFG_NEXT_BCN_EN)
+
#define HWINT_DISABLED 0
#define E2P_PWR_INT_GUARD 8