diff options
| author | Eugene Surovegin | 2005-10-29 12:45:31 -0700 |
|---|---|---|
| committer | Jeff Garzik | 2005-10-29 18:06:54 -0400 |
| commit | 1b195916dd9111bbaf043d0dcfdc5d6908590c6e (patch) | |
| tree | 9b9b8dc2d68dfc1e80855d03e7596475b9291cac /drivers/net | |
| parent | 7ad8a89c2e8a930a902cb0622956b27796c027e5 (diff) | |
[PATCH] PPC 44x EMAC driver: add 440GR support
Add PowerPC 440GR support
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/net/ibm_emac/ibm_emac.h | 3 | ||||
| -rw-r--r-- | drivers/net/ibm_emac/ibm_emac_core.c | 7 | ||||
| -rw-r--r-- | drivers/net/ibm_emac/ibm_emac_mal.h | 2 |
4 files changed, 8 insertions, 6 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6d4f9ceb0a32..97760c1e6b21 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1203,7 +1203,7 @@ config IBM_EMAC_RX_SKB_HEADROOM config IBM_EMAC_PHY_RX_CLK_FIX bool "PHY Rx clock workaround" - depends on IBM_EMAC && (405EP || 440GX || 440EP) + depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR) help Enable this if EMAC attached to a PHY which doesn't generate RX clock if there is no link, if this is the case, you will diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h index d3166da753ef..644edbff4f94 100644 --- a/drivers/net/ibm_emac/ibm_emac.h +++ b/drivers/net/ibm_emac/ibm_emac.h @@ -26,7 +26,8 @@ /* This is a simple check to prevent use of this driver on non-tested SoCs */ #if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \ !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \ - !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) + !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \ + !defined(CONFIG_440GR) #error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK" #endif diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c index 48239e17d351..eb7d69478715 100644 --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c @@ -87,10 +87,11 @@ MODULE_LICENSE("GPL"); */ static u32 busy_phy_map; -#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP)) +#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \ + (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)) /* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us * with PHY RX clock problem. - * 440EP has more sane SDR0_MFR register implementation than 440GX, which + * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which * also allows controlling each EMAC clock */ static inline void EMAC_RX_CLK_TX(int idx) @@ -100,7 +101,7 @@ static inline void EMAC_RX_CLK_TX(int idx) #if defined(CONFIG_405EP) mtdcr(0xf3, mfdcr(0xf3) | (1 << idx)); -#else /* CONFIG_440EP */ +#else /* CONFIG_440EP || CONFIG_440GR */ SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx)); #endif diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h index fb6dfe1197b2..2a2d3b24b037 100644 --- a/drivers/net/ibm_emac/ibm_emac_mal.h +++ b/drivers/net/ibm_emac/ibm_emac_mal.h @@ -32,7 +32,7 @@ * reflect the fact that 40x and 44x have slightly different MALs. --ebs */ #if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \ - defined(CONFIG_440EP) || defined(CONFIG_NP405H) + defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H) #define MAL_VERSION 1 #elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ defined(CONFIG_440SPE) |