diff options
| author | Matt Carlson | 2011-12-14 11:09:57 +0000 |
|---|---|---|
| committer | David S. Miller | 2011-12-15 13:09:10 -0500 |
| commit | 4f272096054b6154e31e850f192eef5782f156c6 (patch) | |
| tree | bac3fb366c8fb4976f23042468f2f83ebe0534cb /drivers/net | |
| parent | c48e074c7c75c0de4652ea5f5bf4e74c8cf4e3dd (diff) | |
tg3: Enable EEE support for capable 10/100 devs
There are some devices in the 57765 ASIC rev that are EEE capable.
Unfortunately the EEE setup code only gets executed if the device is
gigabit capable. This patch fixes the problem.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 19791518f6ae..8a6ea1970ea7 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -3595,18 +3595,17 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) if (err) goto done; - if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) - goto done; - - new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); + if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { + new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); - if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || - tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) - new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; + if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || + tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) + new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; - err = tg3_writephy(tp, MII_CTRL1000, new_adv); - if (err) - goto done; + err = tg3_writephy(tp, MII_CTRL1000, new_adv); + if (err) + goto done; + } if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) goto done; |