diff options
| author | Mugunthan V N | 2013-06-18 15:04:35 +0530 |
|---|---|---|
| committer | David S. Miller | 2013-06-19 18:33:58 -0700 |
| commit | 6d3d76f877ca061911343d5d1650458906fdf0ea (patch) | |
| tree | 769a950b177667066eee283deda5b40bfcf8218f /drivers/net | |
| parent | 2bd470fc08cbbfd4f2e53a620362806620d217ed (diff) | |
drivers: net: cpsw: fix cpsw clock gating issue across suspend/resume
Due to some hardware integration issue, CPSW sliver modules requires a
reset across suspend/resume cycle for a successful clock gating to
CPGMAC (CPSW and Davinci MDIO) in AM335x PG1.0.
This issue is fixed in PG2.x, though to support suspend/resume on PG1.0
this reset is required.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/ti/cpsw.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 2fd69db3c09f..e66a20223abb 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1976,6 +1976,8 @@ static int cpsw_suspend(struct device *dev) if (netif_running(ndev)) cpsw_ndo_stop(ndev); + soft_reset("sliver 0", &priv->slaves[0].sliver->soft_reset); + soft_reset("sliver 1", &priv->slaves[1].sliver->soft_reset); pm_runtime_put_sync(&pdev->dev); return 0; |