diff options
| author | Kishon Vijay Abraham I | 2017-03-13 19:13:22 +0530 |
|---|---|---|
| committer | Bjorn Helgaas | 2017-04-04 08:30:10 -0500 |
| commit | a660083eb06c5bb0ad049377dbd2522e4b1551d6 (patch) | |
| tree | 584103fa6b396db693c314b4dcded93ddc9753f1 /drivers/pci/dwc | |
| parent | 1b497e6493c49bbb55c89f53562f7f853495e90d (diff) | |
PCI: dwc: designware: Add new *ops* for CPU addr fixup
Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init(). While this is okay for
host mode where the address range is fixed, device mode requires different
addresses to be programmed based on the host buffer address. Add a new
ops to get the least 28 bits of the corresponding 32 bit CPU address and
invoke it before programming the address translation unit.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Diffstat (limited to 'drivers/pci/dwc')
| -rw-r--r-- | drivers/pci/dwc/pcie-designware.c | 3 | ||||
| -rw-r--r-- | drivers/pci/dwc/pcie-designware.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 7e1fb7d6643c..3eaf3ccdc118 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, { u32 retries, val; + if (pci->ops->cpu_addr_fixup) + cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr); + if (pci->iatu_unroll_enabled) { dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index cd3b8713fe50..8f3dcb2b099b 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -143,6 +143,7 @@ struct pcie_port { }; struct dw_pcie_ops { + u64 (*cpu_addr_fixup)(u64 cpu_addr); u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); int (*link_up)(struct dw_pcie *pcie); |