diff options
| author | Gabriele Paoloni | 2017-05-23 15:23:59 +0100 |
|---|---|---|
| committer | Bjorn Helgaas | 2017-06-16 19:19:28 -0500 |
| commit | ae6dc7deac2a8639595437af3df5fade878a1601 (patch) | |
| tree | db45ffb492b43e4598bbe417b6e1023ae1131cae /drivers/pci/pcie | |
| parent | a1d5f18cafe6b81696e60ca4901709d2f807362c (diff) | |
PCI/portdrv: Allocate MSI/MSI-X vector for Downstream Port Containment
Currently pcie_port_enable_irq_vec() only allocates MSI/MSI-X vectors for
PME, hotplug, and AER.
The Downstream Port Containment feature also supports MSI/MSI-X interrupts,
so allocate a vector for it, too.
Signed-off-by: Liudongdong <liudongdong3@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
[bhelgaas: changelog, comment]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/pci/pcie')
| -rw-r--r-- | drivers/pci/pcie/portdrv_core.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e00b5da07fef..313a21df1692 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -123,6 +123,33 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask) nvec = max(nvec, entry + 1); } + if (mask & PCIE_PORT_SERVICE_DPC) { + u16 reg16, pos; + + /* + * Per PCIe r4.0 (v0.9), sec 7.9.15.2, the DPC Interrupt + * Message Number in the DPC Capability register indicates + * which MSI/MSI-X vector is used for DPC. + * + * "For MSI, the [DPC Interrupt Message Number] indicates + * the offset between the base Message Data and the + * interrupt message that is generated." + * + * "For MSI-X, the [DPC Interrupt Message Number] indicates + * which MSI-X Table entry is used to generate the + * interrupt message." + */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); + pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16); + entry = reg16 & 0x1f; + if (entry >= nr_entries) + goto out_free_irqs; + + irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry); + + nvec = max(nvec, entry + 1); + } + /* * If nvec is equal to the allocated number of entries, we can just use * what we have. Otherwise, the port has some extra entries not for the |