diff options
| author | Siddharth Vadapalli | 2023-03-31 11:55:20 +0530 |
|---|---|---|
| committer | Vinod Koul | 2023-05-16 20:01:43 +0530 |
| commit | efd658807d3fb838ba79bedecfe45cc838283ac4 (patch) | |
| tree | 89742d6e48525acb88f3caaab616ebba49e1d484 /drivers/phy | |
| parent | 2de2e49b3226cc6252c7dbf1a543e7546db416d3 (diff) | |
phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.
Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
property for J784S4.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331062521.529005-2-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/ti/phy-gmii-sel.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c index c87118cb2af9..fba5c0c0771c 100644 --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -235,6 +235,15 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { .num_qsgmii_main_ports = 2, }; +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = { + .use_of_data = true, + .regfields = phy_gmii_sel_fields_am654, + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .num_ports = 8, + .num_qsgmii_main_ports = 2, +}; + static const struct of_device_id phy_gmii_sel_id_table[] = { { .compatible = "ti,am3352-phy-gmii-sel", @@ -264,6 +273,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = { .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", .data = &phy_gmii_sel_cpsw9g_soc_j721e, }, + { + .compatible = "ti,j784s4-cpsw9g-phy-gmii-sel", + .data = &phy_gmii_sel_cpsw9g_soc_j784s4, + }, {} }; MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); |