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authorDaniel Kurtz2018-03-12 10:45:30 -0600
committerLinus Walleij2018-03-26 11:09:49 +0200
commit4c1de0414a134086e9587dc9e7c85cd557c83034 (patch)
tree557a64c93cb81f78c1c07e40f74c213006822709 /drivers/pinctrl/uniphier
parent44edff1bbc48595a041f65a725203763e3590a73 (diff)
pinctrl/amd: poll InterruptEnable bits in enable_irq
In certain cases interrupt enablement will be delayed relative to when the InterruptEnable bits are written. One example of this is when a GPIO's "debounce" logice is first enabled. After enabling debounce, there is a 900 us "warm up" period during which InterruptEnable[0] (bit 11) will read as 0 despite being written 1. During this time InterruptSts will not be updated, nor will interrupts be delivered, even if the GPIO's interrupt configuration has been written to the register. To work around this delay, poll the InterruptEnable bits after setting them to ensure interrupts have truly been enabled in hardware before returning from the irq_enable handler. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/uniphier')
0 files changed, 0 insertions, 0 deletions