diff options
| author | Paul Cercueil | 2020-01-07 00:27:10 +0100 |
|---|---|---|
| committer | Linus Walleij | 2020-01-07 13:57:17 +0100 |
| commit | f831f93af676587c938459f7f0833707f3b623c1 (patch) | |
| tree | f00fabbd33436b0f5f76f2c695f4e722d0670799 /drivers/pinctrl | |
| parent | 5ffdbb7ec9facf6d9854c67960f7ba3a4de86f58 (diff) | |
pinctrl: ingenic: Factorize irq_set_type function
Simplify the code of the driver's irq_set_type() function by doing some
factorization. The behaviour is unchanged.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-5-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/pinctrl-ingenic.c | 64 |
1 files changed, 24 insertions, 40 deletions
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 7f73f27cce91..419717fc7793 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1676,58 +1676,42 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, u8 offset, unsigned int type) { u8 reg1, reg2; - - if (jzgc->jzpc->info->version >= ID_JZ4760) { - reg1 = JZ4760_GPIO_PAT1; - reg2 = JZ4760_GPIO_PAT0; - } else { - reg1 = JZ4740_GPIO_TRIG; - reg2 = JZ4740_GPIO_DIR; - } + bool val1, val2; switch (type) { case IRQ_TYPE_EDGE_RISING: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); - } + val1 = val2 = true; break; case IRQ_TYPE_EDGE_FALLING: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); - } + val1 = false; + val2 = true; break; case IRQ_TYPE_LEVEL_HIGH: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); - } + val1 = true; + val2 = false; break; case IRQ_TYPE_LEVEL_LOW: default: - if (jzgc->jzpc->info->version >= ID_X1000) { - ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); - ingenic_gpio_shadow_set_bit_load(jzgc); - } else { - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); - } + val1 = val2 = false; break; } + + if (jzgc->jzpc->info->version >= ID_JZ4760) { + reg1 = JZ4760_GPIO_PAT1; + reg2 = JZ4760_GPIO_PAT0; + } else { + reg1 = JZ4740_GPIO_TRIG; + reg2 = JZ4740_GPIO_DIR; + } + + if (jzgc->jzpc->info->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, val1); + ingenic_gpio_set_bit(jzgc, reg1, offset, val2); + } } static void ingenic_gpio_irq_mask(struct irq_data *irqd) |