diff options
author | Linus Torvalds | 2020-12-15 15:51:10 -0800 |
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committer | Linus Torvalds | 2020-12-15 15:51:10 -0800 |
commit | 605ea5aafe1341ac9b2144516f898ac78ad49c40 (patch) | |
tree | 0b5daead68196953f961902571f74aa7900430bc /drivers/platform/chrome | |
parent | 2dda5700ef6af806e0358f63d81eb436a0d280fa (diff) | |
parent | 3e98a021cc85e7d52acdd1eae8a988e975ec5bf9 (diff) |
Merge tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"The big change this release has been some excellent work from Lukas
Wunner which closes a bunch of holes in the cleanup paths for drivers,
mainly introduced as a result of devm conversions causing bad
interactions with the support SPI has for allocating the bus and
driver data together.
Together with some of the other work done it feels like we've turned
the corner on several long standing pain points with the API.
Summary:
- Many cleanups around probe/remove and error handling from Lukas
Wunner and Uwe Kleine-König, and further fixes around PM from Zhang
Qilong.
- Provide a mask for which bits of the mode can safely be configured
by drivers and use that to fix an issue with the ADS7846 driver.
- Documentation of the expected interactions between SPI and GPIO
level chip select polarity configuration from H. Nikolaus Schaller,
hopefully we're pretty much at the end of sorting out the
interactions there. Thanks to Nikolaus, Sven Van Asbroeck and Linus
Walleij for this.
- DMA support for Allwinner sun6i controllers.
- Support for Canaan K210 Designware implementations and Intel Adler
Lake"
* tag 'spi-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (69 commits)
spi: dt-bindings: clarify CS behavior for spi-cs-high and gpio descriptors
spi: Limit the spi device max speed to controller's max speed
spi: spi-geni-qcom: Use the new method of gpio CS control
platform/chrome: cros_ec_spi: Drop bits_per_word assignment
platform/chrome: cros_ec_spi: Don't overwrite spi::mode
spi: dw: Add support for the Canaan K210 SoC SPI
spi: dw: Add support for 32-bits max xfer size
dt-bindings: spi: dw-apb-ssi: Add Canaan K210 SPI controller
spi: Update DT binding docs to support SiFive FU740 SoC
spi: atmel-quadspi: Fix use-after-free on unbind
spi: npcm-fiu: Disable clock in probe error path
spi: ar934x: Don't leak SPI master in probe error path
spi: mt7621: Don't leak SPI master in probe error path
spi: mt7621: Disable clock in probe error path
media: netup_unidvb: Don't leak SPI master in probe error path
spi: sc18is602: Don't leak SPI master in probe error path
spi: rb4xx: Don't leak SPI master in probe error path
spi: gpio: Don't leak SPI master in probe error path
spi: spi-mtk-nor: Don't leak SPI master in probe error path
spi: mxic: Don't leak SPI master in probe error path
...
Diffstat (limited to 'drivers/platform/chrome')
-rw-r--r-- | drivers/platform/chrome/cros_ec_spi.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/platform/chrome/cros_ec_spi.c b/drivers/platform/chrome/cros_ec_spi.c index dfa1f816a45f..14c4046fa04d 100644 --- a/drivers/platform/chrome/cros_ec_spi.c +++ b/drivers/platform/chrome/cros_ec_spi.c @@ -741,8 +741,6 @@ static int cros_ec_spi_probe(struct spi_device *spi) struct cros_ec_spi *ec_spi; int err; - spi->bits_per_word = 8; - spi->mode = SPI_MODE_0; spi->rt = true; err = spi_setup(spi); if (err < 0) |