diff options
| author | Wayne Boyer | 2010-05-10 09:14:07 -0700 |
|---|---|---|
| committer | James Bottomley | 2010-05-24 11:11:05 -0500 |
| commit | 7be96900a2a662c67403559acd250f011b1d70db (patch) | |
| tree | f7d3aa2ffb317f35fea7e37dd0982bb140dde3c9 /drivers/scsi/ipr.c | |
| parent | 96d21f00ab59c9f27fad191d12a2ccfeff3c9108 (diff) | |
[SCSI] ipr: fix a register read to use the correct address for 64 bit adapters
Fix ipr_reset_enable_ioa() to read the correct IOA to host interrupt register
address for 64 bit adapters. We need to read the lower 32 bits, not the upper
32 bits.
Also change the write of the 64 bit mask value to a single writeq instead
of two writel calls.
Finally, use the correct u8 type for the type field in the ipr_resource_entry
structure.
Signed-off-by: Wayne Boyer <wayneb@linux.vnet.ibm.com>
Acked-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: James Bottomley <James.Bottomley@suse.de>
Diffstat (limited to 'drivers/scsi/ipr.c')
| -rw-r--r-- | drivers/scsi/ipr.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 8c2f4c4041c1..2f280d08fcc6 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -7187,13 +7187,14 @@ static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd) { struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg; volatile u32 int_reg; + volatile u64 maskval; ENTER; ipr_cmd->job_step = ipr_ioafp_identify_hrrq; ipr_init_ioa_mem(ioa_cfg); ioa_cfg->allow_interrupts = 1; - int_reg = readl(ioa_cfg->regs.sense_interrupt_reg); + int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32); if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) { writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED), @@ -7205,9 +7206,12 @@ static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd) /* Enable destructive diagnostics on IOA */ writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32); - writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32); - if (ioa_cfg->sis64) - writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_mask_reg); + if (ioa_cfg->sis64) { + maskval = IPR_PCII_IPL_STAGE_CHANGE; + maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS; + writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg); + } else + writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32); int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg); |