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authorDong Aisheng2017-03-23 12:53:19 +0800
committerShawn Guo2017-03-24 13:41:51 +0800
commit3a317f523570adfc9c5bf6d65dc4f831dada97b9 (patch)
tree81bef9bc3849470b90f6ac85759949ee1cbf6c08 /drivers/soc
parent55b0baa2542f1dbaf33989eab5a26a23a8aca345 (diff)
soc: imx: gpc: fix the wrong using of regmap cache
Without providing the proper reg_defaults, the regmap registers first read out may be always 0 if enabling cache, which results in the following issue we met. e.g. During driver probe in imx6_pm_domain_power_on(): regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val); The PGC_PUPSCR register val is always 0 but it's actually 0xf01 in HW. Since GPC registers are tightly related to CPU bring up and may be changed in bootloader, we don't want to provide defaults. And the cache really does not save too much for GPC module. Therefore, simply disable cache to fix the issue and make life easy. Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Fixes: 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/imx/gpc.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c
index c9bfdfd783d0..7e6a672bf5f4 100644
--- a/drivers/soc/imx/gpc.c
+++ b/drivers/soc/imx/gpc.c
@@ -289,22 +289,12 @@ static bool imx_gpc_readable_reg(struct device *dev, unsigned int reg)
return (reg % 4 == 0) && (reg <= 0x2ac);
}
-static bool imx_gpc_volatile_reg(struct device *dev, unsigned int reg)
-{
- if (reg == GPC_CNTR)
- return true;
-
- return false;
-}
-
static const struct regmap_config imx_gpc_regmap_config = {
- .cache_type = REGCACHE_FLAT,
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.readable_reg = imx_gpc_readable_reg,
- .volatile_reg = imx_gpc_volatile_reg,
.max_register = 0x2ac,
};