diff options
| author | Arnd Bergmann | 2016-07-14 15:26:44 +0200 |
|---|---|---|
| committer | Arnd Bergmann | 2016-07-14 15:26:44 +0200 |
| commit | f8c6d88b2c874295f49b9ad1ca0826b9a8ef3180 (patch) | |
| tree | 6ba625358c04f8aa9d747a60416eed2b366ccee1 /drivers/soc | |
| parent | f1844aca29025bb436bfc4f872456b832632df56 (diff) | |
| parent | aec6341e2ac76ea8703642e83535f216b8866162 (diff) | |
Merge tag 'samsung-drivers-4.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers
Merge "Samsung drivers/soc update for v4.8, part 3" into next/drivers:
1. Fix size of allocation for Exynos SROM registers (too much was allocated).
2. Constify fix.
* tag 'samsung-drivers-4.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
soc: samsung: pmu: Constify arrays with PMU data
memory: samsung: exynos-srom: Fix wrong count of registers
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/samsung/exynos3250-pmu.c | 2 | ||||
| -rw-r--r-- | drivers/soc/samsung/exynos5420-pmu.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/soc/samsung/exynos3250-pmu.c b/drivers/soc/samsung/exynos3250-pmu.c index 20b3ab8aa790..af2f54e14b83 100644 --- a/drivers/soc/samsung/exynos3250-pmu.c +++ b/drivers/soc/samsung/exynos3250-pmu.c @@ -14,7 +14,7 @@ #include "exynos-pmu.h" -static struct exynos_pmu_conf exynos3250_pmu_config[] = { +static const struct exynos_pmu_conf exynos3250_pmu_config[] = { /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */ { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, diff --git a/drivers/soc/samsung/exynos5420-pmu.c b/drivers/soc/samsung/exynos5420-pmu.c index b962fb6a5d22..3f2c64180ef8 100644 --- a/drivers/soc/samsung/exynos5420-pmu.c +++ b/drivers/soc/samsung/exynos5420-pmu.c @@ -17,7 +17,7 @@ #include "exynos-pmu.h" -static struct exynos_pmu_conf exynos5420_pmu_config[] = { +static const struct exynos_pmu_conf exynos5420_pmu_config[] = { /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, |