diff options
| author | Serge Semin | 2020-10-08 02:54:59 +0300 |
|---|---|---|
| committer | Mark Brown | 2020-10-08 23:00:13 +0100 |
| commit | 82d02944d238a6fdac729d135623b1d88ca8cbd6 (patch) | |
| tree | f92956081f49bc7fc44e44b75c401949c139f0bc /drivers/spi | |
| parent | ddcc2733c1591c137f7ce60f24ba5401c295427f (diff) | |
spi: dw: Perform IRQ setup in a dedicated function
In order to make the transfer_one() callback method more readable and
for unification with the DMA-based transfer, let's detach the IRQ setup
procedure into a dedicated function. While at it rename the IRQ-based
transfer handler function to be dw_spi-prefixe and looking more like the
DMA-related one.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20201007235511.4935-11-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-dw-core.c | 41 |
1 files changed, 23 insertions, 18 deletions
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 4a45610c85f1..e7ffcfff6594 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -178,7 +178,7 @@ static void int_error_stop(struct dw_spi *dws, const char *msg) spi_finalize_current_transfer(dws->master); } -static irqreturn_t interrupt_transfer(struct dw_spi *dws) +static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws) { u16 irq_status = dw_readl(dws, DW_SPI_ISR); @@ -315,6 +315,27 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, } EXPORT_SYMBOL_GPL(dw_spi_update_config); +static void dw_spi_irq_setup(struct dw_spi *dws) +{ + u16 level; + u8 imask; + + /* + * Originally Tx and Rx data lengths match. Rx FIFO Threshold level + * will be adjusted at the final stage of the IRQ-based SPI transfer + * execution so not to lose the leftover of the incoming data. + */ + level = min_t(u16, dws->fifo_len / 2, dws->tx_len); + dw_writel(dws, DW_SPI_TXFTLR, level); + dw_writel(dws, DW_SPI_RXFTLR, level - 1); + + imask = SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI | + SPI_INT_RXFI; + spi_umask_intr(dws, imask); + + dws->transfer_handler = dw_spi_transfer_handler; +} + static int dw_spi_transfer_one(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *transfer) { @@ -324,8 +345,6 @@ static int dw_spi_transfer_one(struct spi_controller *master, .dfs = transfer->bits_per_word, .freq = transfer->speed_hz, }; - u8 imask = 0; - u16 txlevel = 0; int ret; dws->dma_mapped = 0; @@ -358,21 +377,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, return ret; } } else { - /* - * Originally Tx and Rx data lengths match. Rx FIFO Threshold level - * will be adjusted at the final stage of the IRQ-based SPI transfer - * execution so not to lose the leftover of the incoming data. - */ - txlevel = min_t(u16, dws->fifo_len / 2, dws->tx_len); - dw_writel(dws, DW_SPI_TXFTLR, txlevel); - dw_writel(dws, DW_SPI_RXFTLR, txlevel - 1); - - /* Set the interrupt mask */ - imask |= SPI_INT_TXEI | SPI_INT_TXOI | - SPI_INT_RXUI | SPI_INT_RXOI | SPI_INT_RXFI; - spi_umask_intr(dws, imask); - - dws->transfer_handler = interrupt_transfer; + dw_spi_irq_setup(dws); } spi_enable_chip(dws, 1); |