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authorMark Brown2020-07-29 14:51:58 +0100
committerMark Brown2020-07-29 14:51:58 +0100
commit8ade0c2fabd3f15e334cc1b8e3780477ae7b9662 (patch)
tree5fbbe26d10864f39b23efc318b788ebffbcb050e /drivers/spi
parent92ed301919932f777713b9172e525674157e983d (diff)
parentaffe93dd5b35bb0e7b0aa0505ae432dd0ac72c3f (diff)
Merge remote-tracking branch 'spi/for-5.8' into spi-linus
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-dw-dma.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 5986c520b196..bb390ff67d1d 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -372,8 +372,20 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
u16 imr = 0, dma_ctrl = 0;
+ /*
+ * Having a Rx DMA channel serviced with higher priority than a Tx DMA
+ * channel might not be enough to provide a well balanced DMA-based
+ * SPI transfer interface. There might still be moments when the Tx DMA
+ * channel is occasionally handled faster than the Rx DMA channel.
+ * That in its turn will eventually cause the SPI Rx FIFO overflow if
+ * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's
+ * cleared by the Rx DMA channel. In order to fix the problem the Tx
+ * DMA activity is intentionally slowed down by limiting the SPI Tx
+ * FIFO depth with a value twice bigger than the Tx burst length
+ * calculated earlier by the dw_spi_dma_maxburst_init() method.
+ */
dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
- dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
+ dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
if (xfer->tx_buf)
dma_ctrl |= SPI_DMA_TDMAE;