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authorBartlomiej Zolnierkiewicz2014-10-03 18:17:17 +0200
committerEduardo Valentin2014-11-02 23:02:49 -0400
commitb835ced1fd05c43bd4a706050963678bc6e95bc7 (patch)
tree1933e4f19ff68cea859b097193a69c02607f00f0 /drivers/thermal/samsung/exynos_tmu_data.h
parentc2aad93c7edd5e1bc26cc1d80c1c00a954f01946 (diff)
thermal: exynos: fix IRQ clearing on TMU initialization
* Factor out code for clearing raised IRQs from exynos_tmu_work() to exynos_tmu_clear_irqs(). * Add a comment about documentation bugs to exynos_tmu_clear_irqs(). [ The documentation for Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly states that INTCLEAR register has a different placing of bits responsible for FALL IRQs than INTSTAT register. Exynos5420 and Exynos5440 documentation is correct (Exynos4210 doesn't support FALL IRQs at all). ] * Use exynos_tmu_clear_irqs() in exynos_tmu_initialize() instead of open-coded code trying to clear IRQs according to predefined masks. After this change exynos_tmu_initialize() just clears IRQs that are raised like it is already done in exynos_tmu_work(). As a nice side-effect the code now uses the correct offset (16 instead of 12) for bits responsible for clearing FALL IRQs in INTCLEAR register on Exynos3250, Exynos4412 and Exynos5250. * Remove no longer needed intclr_rise_[mask,shift] and intclr_fall_[mask,shift] fields from struct exynos_tmu_registers. * Remove no longer needed defines. This patch has been tested on Exynos4412 and Exynos5420 SoCs. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'drivers/thermal/samsung/exynos_tmu_data.h')
-rw-r--r--drivers/thermal/samsung/exynos_tmu_data.h15
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 4b8f33c85b35..65e2ea6a9579 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -46,8 +46,6 @@
#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
-#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
-
/* Exynos5250, Exynos4412, Exynos3250 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON2 0x14
#define EXYNOS_THD_TEMP_RISE 0x50
@@ -57,12 +55,6 @@
#define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
#define EXYNOS_TRIMINFO_25_SHIFT 0
#define EXYNOS_TRIMINFO_85_SHIFT 8
-#define EXYNOS_TMU_RISE_INT_MASK 0x111
-#define EXYNOS_TMU_RISE_INT_SHIFT 0
-#define EXYNOS_TMU_FALL_INT_MASK 0x111
-#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
-#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT 16
-#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT 4
#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
@@ -87,10 +79,6 @@
#define EXYNOS5260_TMU_REG_INTEN 0xC0
#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
-#define EXYNOS5260_TMU_CLEAR_RISE_INT 0x1111
-#define EXYNOS5260_TMU_CLEAR_FALL_INT (0x1111 << 16)
-#define EXYNOS5260_TMU_RISE_INT_MASK 0x1111
-#define EXYNOS5260_TMU_FALL_INT_MASK 0x1111
#define EXYNOS5260_EMUL_CON 0x100
/* Exynos4412 specific */
@@ -112,9 +100,6 @@
#define EXYNOS5440_TMU_IRQ_STATUS 0x000
#define EXYNOS5440_TMU_PMIN 0x004
-#define EXYNOS5440_TMU_RISE_INT_MASK 0xf
-#define EXYNOS5440_TMU_RISE_INT_SHIFT 0
-#define EXYNOS5440_TMU_FALL_INT_MASK 0xf
#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2