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authorKarthikeyan Ramasubramanian2018-05-03 14:14:37 -0600
committerGreg Kroah-Hartman2018-05-14 13:44:55 +0200
commit7fb5b8800194c0d9a5d2aa8b3983cf7bc615b3ea (patch)
tree6c72d1f2f6cdae7b3b326b316db06ba0001e51f9 /drivers/tty
parentf73717506151742ec580d52a6e427e333f853eef (diff)
tty: serial: qcom_geni_serial: Remove unnecessary memory barrier
While initiating TX, only the register reads need to be ordered. The register write order either is achieved due to data dependency or is not required. Use readl to achieve the read order and remove the unnecessary barrier. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/qcom_geni_serial.c16
1 files changed, 7 insertions, 9 deletions
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index d114b67be409..3e9de6c780d3 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -417,20 +417,18 @@ static void qcom_geni_serial_start_tx(struct uart_port *uport)
u32 status;
if (port->xfer_mode == GENI_SE_FIFO) {
- status = readl_relaxed(uport->membase + SE_GENI_STATUS);
+ /*
+ * readl ensures reading & writing of IRQ_EN register
+ * is not re-ordered before checking the status of the
+ * Serial Engine.
+ */
+ status = readl(uport->membase + SE_GENI_STATUS);
if (status & M_GENI_CMD_ACTIVE)
return;
if (!qcom_geni_serial_tx_empty(uport))
return;
- /*
- * Ensure writing to IRQ_EN & watermark registers are not
- * re-ordered before checking the status of the Serial
- * Engine and TX FIFO
- */
- mb();
-
irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
@@ -894,7 +892,7 @@ out_restart_rx:
static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
{
- return !readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
+ return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
}
#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE