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authorArtur Petrosyan2021-04-13 11:36:52 +0400
committerGreg Kroah-Hartman2021-04-13 12:25:12 +0200
commitd37b939cf41f6a211d6c5611915c5dd4552cd935 (patch)
tree9527934e3e9941c73b8f5890fd2f3cceac761017 /drivers/usb/dwc2
parent5f9e60c06175c3525c2f7ae1d6807f7d6c61efe3 (diff)
usb: dwc2: Update enter clock gating when port is suspended
Updates the implementation of entering clock gating mode when core receives port suspend. Instead of setting the required bit fields of the registers inline, called the "dwc2_host_enter_clock_gating()" function. Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@synopsys.com> Link: https://lore.kernel.org/r/20210413073653.9F493A0094@mailhost.synopsys.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/dwc2')
-rw-r--r--drivers/usb/dwc2/hcd.c19
1 files changed, 4 insertions, 15 deletions
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 27f030d5de54..e1225fe6c61a 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -3298,7 +3298,6 @@ static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
{
unsigned long flags;
- u32 hprt0;
u32 pcgctl;
u32 gotgctl;
int ret = 0;
@@ -3323,22 +3322,12 @@ int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
break;
case DWC2_POWER_DOWN_PARAM_HIBERNATION:
case DWC2_POWER_DOWN_PARAM_NONE:
- default:
- hprt0 = dwc2_read_hprt0(hsotg);
- hprt0 |= HPRT0_SUSP;
- dwc2_writel(hsotg, hprt0, HPRT0);
- hsotg->bus_suspended = true;
/*
- * If power_down is supported, Phy clock will be suspended
- * after registers are backuped.
+ * If not hibernation nor partial power down are supported,
+ * clock gating is used to save power.
*/
- if (!hsotg->params.power_down) {
- /* Suspend the Phy Clock */
- pcgctl = dwc2_readl(hsotg, PCGCTL);
- pcgctl |= PCGCTL_STOPPCLK;
- dwc2_writel(hsotg, pcgctl, PCGCTL);
- udelay(10);
- }
+ dwc2_host_enter_clock_gating(hsotg);
+ break;
}
/* For HNP the bus must be suspended for at least 200ms */