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authorArnd Bergmann2012-03-16 20:25:17 +0000
committerArnd Bergmann2012-03-16 20:25:17 +0000
commita94c7b0a8f31a8bcf3b136d469f7eb6b6b57bb78 (patch)
treecac33ce0abaaeb56b6e08a396cb7ff4e3e3b8f61 /drivers/usb
parentd4ef467aea0fdcd5e75a4bbfaf97e579bbe532f3 (diff)
parent9652e8bd16e73f7a34cabf1ab114aaa5c97db660 (diff)
Merge branch 'spear/dt' into next/dt2
* spear/dt: ARM: SPEAr600: Add device-tree support to SPEAr600 boards (update to v3.3-rc7) Conflicts: arch/arm/mach-spear6xx/spear6xx.c arch/arm/mach-vexpress/Kconfig The conflicts are between the previous contents of the next/dt2 branch and upstream changes from v3.3-rc7. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/host/ehci-fsl.c11
-rw-r--r--drivers/usb/host/ehci-fsl.h1
2 files changed, 2 insertions, 10 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index c26a82e83f6e..b556a72264d1 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -239,7 +239,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci,
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
}
-static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
+static void ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
@@ -299,19 +299,12 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
#endif
out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
}
-
- if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & CTRL_PHY_CLK_VALID)) {
- printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
- return -ENODEV;
- }
- return 0;
}
/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_fsl_reinit(struct ehci_hcd *ehci)
{
- if (ehci_fsl_usb_setup(ehci))
- return -ENODEV;
+ ehci_fsl_usb_setup(ehci);
ehci_port_power(ehci, 0);
return 0;
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index bdf43e2adc51..491806221165 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -45,6 +45,5 @@
#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
-#define CTRL_PHY_CLK_VALID (1 << 17)
#define SNOOP_SIZE_2GB 0x1e
#endif /* _EHCI_FSL_H */