diff options
| author | Thinh Nguyen | 2018-03-16 15:33:48 -0700 |
|---|---|---|
| committer | Felipe Balbi | 2018-03-22 10:48:46 +0200 |
| commit | fab3833338779e1e668bd58d1f76d601657304b8 (patch) | |
| tree | a7071ba2b0f8b27bfadc3600040378fdf2b5bd65 /drivers/usb | |
| parent | cabdf83dadfb3d83eec31e0f0638a92dbd716435 (diff) | |
usb: dwc3: Add SoftReset PHY synchonization delay
From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/dwc3/core.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index e8890c0201a5..5491d9678d70 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -244,7 +244,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) do { reg = dwc3_readl(dwc->regs, DWC3_DCTL); if (!(reg & DWC3_DCTL_CSFTRST)) - return 0; + goto done; udelay(1); } while (--retries); @@ -253,6 +253,17 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) phy_exit(dwc->usb2_generic_phy); return -ETIMEDOUT; + +done: + /* + * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, + * we must wait at least 50ms before accessing the PHY domain + * (synchronization delay). DWC_usb31 programming guide section 1.3.2. + */ + if (dwc3_is_usb31(dwc)) + msleep(50); + + return 0; } /* |