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author | Vincent Whitchurch | 2021-06-30 12:22:32 +0200 |
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committer | Ulf Hansson | 2021-08-04 12:41:20 +0200 |
commit | 25f8203b4be1937c4939bb98623e67dcfd7da4d1 (patch) | |
tree | a96c16d9a6244eddfecbfeaaa35f6468db5be0e7 /drivers/watchdog/rn5t618_wdt.c | |
parent | c500bee1c5b2f1d59b1081ac879d73268ab0ff17 (diff) |
mmc: dw_mmc: Fix hang on data CRC error
When a Data CRC interrupt is received, the driver disables the DMA, then
sends the stop/abort command and then waits for Data Transfer Over.
However, sometimes, when a data CRC error is received in the middle of a
multi-block write transfer, the Data Transfer Over interrupt is never
received, and the driver hangs and never completes the request.
The driver sets the BMOD.SWR bit (SDMMC_IDMAC_SWRESET) when stopping the
DMA, but according to the manual CMD.STOP_ABORT_CMD should be programmed
"before assertion of SWR". Do these operations in the recommended
order. With this change the Data Transfer Over is always received
correctly in my tests.
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20210630102232.16011-1-vincent.whitchurch@axis.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/watchdog/rn5t618_wdt.c')
0 files changed, 0 insertions, 0 deletions