diff options
| author | Thibaut VARENE | 2007-03-12 02:31:30 -0700 |
|---|---|---|
| committer | Jeff Garzik | 2007-04-28 11:00:58 -0400 |
| commit | eb117b1786804f2e128b871879ffe8f6a2701378 (patch) | |
| tree | 9f2788c5abbe5eff39495a53bbf9bef34d318ca1 /drivers | |
| parent | b3bff39a2b3574542f5007e19038393dfdd64c85 (diff) | |
TULIP: Natsemi dp83840a PHY fix
Fix a problem with Tulip 21142 HP branded PCI cards (PN#: B5509-66001),
which feature a NatSemi DP83840A PHY.
Without that patch, it is impossible to properly initialize the card's PHY,
and it's thus impossible to monitor/configure it.
[VAL: I'm happy with the 1.5 ms max delay; it doesn't seem excessive.]
Signed-off-by: Thibaut VARENE <varenet@parisc-linux.org>
Cc: Jeff Garzik <jgarzik@pobox.com>
Acked-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Valerie Henson <val_henson@linux.intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/tulip/media.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c index 1594160a0f62..b56256636543 100644 --- a/drivers/net/tulip/media.c +++ b/drivers/net/tulip/media.c @@ -263,11 +263,27 @@ void tulip_select_media(struct net_device *dev, int startup) u16 *reset_sequence = &((u16*)(p+3))[init_length]; int reset_length = p[2 + init_length*2]; misc_info = reset_sequence + reset_length; - if (startup) + if (startup) { + int timeout = 10; /* max 1 ms */ for (i = 0; i < reset_length; i++) iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); + + /* flush posted writes */ + ioread32(ioaddr + CSR15); + + /* Sect 3.10.3 in DP83840A.pdf (p39) */ + udelay(500); + + /* Section 4.2 in DP83840A.pdf (p43) */ + /* and IEEE 802.3 "22.2.4.1.1 Reset" */ + while (timeout-- && + (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) + udelay(100); + } for (i = 0; i < init_length; i++) iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); + + ioread32(ioaddr + CSR15); /* flush posted writes */ } else { u8 *init_sequence = p + 2; u8 *reset_sequence = p + 3 + init_length; |