diff options
| author | Alex Deucher | 2011-10-12 18:44:33 -0400 |
|---|---|---|
| committer | Dave Airlie | 2011-10-18 10:16:33 +0100 |
| commit | 09cc6506f9e234b2ead60398ebb88c4b44421a93 (patch) | |
| tree | 2316509850a5c4e6882f64557afbea4a76a409b8 /drivers | |
| parent | 3a6dea31453a101bd5e9e9c89a79f4fcb6b0342e (diff) | |
drm/radeon/kms/DCE4.1: ss is not supported on the internal pplls
It's handled via external clock. It should already be protected
by the external ss flag, but add an explicit check just in case.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index c742944d3805..a515b2a09d85 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -466,7 +466,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, return; } args.v2.ucEnable = enable; - if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) + if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) args.v2.ucEnable = ATOM_DISABLE; } else if (ASIC_IS_DCE3(rdev)) { args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |