diff options
| author | Yoshihiro Shimoda | 2019-08-08 15:19:01 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven | 2019-08-12 15:55:15 +0200 |
| commit | 1d4ba593d02e8ec41c2baaabdce9f62b71062dc7 (patch) | |
| tree | f7c469faa0af08a49e3efd2e3193045d55c4f38f /drivers | |
| parent | 625efea83a7c37d281c6a90526813a1366929d24 (diff) | |
pinctrl: sh-pfc: Add new flags into struct sh_pfc_pin_config
To clean/modify the code up later, this patch just adds new flags
"mux_set" and "gpio_enabled" into the struct sh_pfc_pin_config.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pinctrl/sh-pfc/pinctrl.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 2824be4eb887..864da24394d6 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -27,6 +27,8 @@ struct sh_pfc_pin_config { u32 type; + bool mux_set; + bool gpio_enabled; }; struct sh_pfc_pinctrl { @@ -364,7 +366,15 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, for (i = 0; i < grp->nr_pins; ++i) { ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) - break; + goto done; + } + + /* All group pins are configured, mark the pins as mux_set */ + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + cfg->mux_set = true; } done: @@ -405,6 +415,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, } cfg->type = PINMUX_TYPE_GPIO; + cfg->gpio_enabled = true; ret = 0; @@ -426,6 +437,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); cfg->type = PINMUX_TYPE_NONE; + cfg->gpio_enabled = false; spin_unlock_irqrestore(&pfc->lock, flags); } |