diff options
| author | Vadim Pasternak | 2021-10-02 12:36:09 +0300 |
|---|---|---|
| committer | Hans de Goede | 2021-10-19 10:57:20 +0200 |
| commit | 249606d37d205eb2f9a6f2c8ecb8bd77b53e5d3e (patch) | |
| tree | 6016fd7c38280a467cefd99ae1459efa9c2c49ba /drivers | |
| parent | 5b0a315c3db548646e2cc9707d8a82d818a3c956 (diff) | |
platform/x86: mlx-platform: Add support for multiply cooling devices
Add new registers to support systems with multiply cooling devices.
Modular systems support up-to four cooling devices. This capability
is detected according to the registers initial setting.
Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
Reviewed-by: Michael <michaelsh@nvidia.com>
Link: https://lore.kernel.org/r/20211002093609.3771576-1-vadimp@nvidia.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/platform/x86/mlx-platform.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c index 2ab499686564..7606165980c3 100644 --- a/drivers/platform/x86/mlx-platform.c +++ b/drivers/platform/x86/mlx-platform.c @@ -120,12 +120,15 @@ #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 +#define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 +#define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 +#define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 @@ -3415,6 +3418,18 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, }, { + .label = "pwm2", + .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, + }, + { + .label = "pwm3", + .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, + }, + { + .label = "pwm4", + .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, + }, + { .label = "tacho1", .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, .mask = GENMASK(7, 0), @@ -3803,6 +3818,9 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: return true; } @@ -3902,6 +3920,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: @@ -4014,6 +4035,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: @@ -4069,6 +4093,9 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, + { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, |