diff options
| author | Jingoo Han | 2012-09-12 16:52:09 +0900 |
|---|---|---|
| committer | Florian Tobias Schandinat | 2012-09-22 21:40:28 +0000 |
| commit | 5fdc62ca62d7e896ef8ad64b68127e81eb3bdc3f (patch) | |
| tree | 6141bd247024f19ff9e0d4abfc3768da16fff2bd /drivers | |
| parent | e3c02009003eebf84f7c56c7f330521553c8d299 (diff) | |
video: exynos_dp: increase AUX channel voltage level
The value of AUX channel differential amplitude current is changed
from 8 mA to 16 mA, in order to increase AUX channel voltage level.
In this case, AUX channel voltage level can be changed from 400 mV
to 800 mV, when resistance between AUX TX and RX is 100 ohm.
According to DP spec, although the normative voltage level is 390 mV,
the informative voltage level is 430 mV. So, 800 mV can be helpful
to improve voltage margin of AUX channel.
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/exynos/exynos_dp_reg.c | 2 | ||||
| -rw-r--r-- | drivers/video/exynos/exynos_dp_reg.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 365be69d9b5c..3f5ca8a0d5ea 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c @@ -77,7 +77,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp) writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | - TX_CUR1_2X | TX_CUR_8_MA; + TX_CUR1_2X | TX_CUR_16_MA; writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); reg = CH3_AMP_400_MV | CH2_AMP_400_MV | diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 9e9af50d7da3..1f2f014cfe88 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -187,7 +187,7 @@ #define PD_RING_OSC (0x1 << 6) #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) #define TX_CUR1_2X (0x1 << 2) -#define TX_CUR_8_MA (0x2 << 0) +#define TX_CUR_16_MA (0x3 << 0) /* EXYNOS_DP_TX_AMP_TUNING_CTL */ #define CH3_AMP_400_MV (0x0 << 24) |