diff options
| author | Harald Welte | 2009-05-15 16:00:32 +1000 |
|---|---|---|
| committer | Herbert Xu | 2009-06-02 14:04:53 +1000 |
| commit | 858576bdc5d65edf1fffd2e65b2165ec1dc68486 (patch) | |
| tree | fbece7a0b0ad73218ca24071ca8f0e17584e0963 /drivers | |
| parent | 608d1cd5d375580a49d01b5ed1f9944f5141ae19 (diff) | |
hwrng: via_rng - Support VIA Nano hardware RNG
The VIA Nano CPU supports the same XSTORE instruction based RNG,
but it lacks the MSR present in earlier CPUs.
Signed-off-by: Harald Welte <HaraldWelte@viatech.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/char/hw_random/via-rng.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c index 02ee63906713..794aacb715c1 100644 --- a/drivers/char/hw_random/via-rng.c +++ b/drivers/char/hw_random/via-rng.c @@ -132,6 +132,19 @@ static int via_rng_init(struct hwrng *rng) struct cpuinfo_x86 *c = &cpu_data(0); u32 lo, hi, old_lo; + /* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG + * is always enabled if CPUID rng_en is set. There is no + * RNG configuration like it used to be the case in this + * register */ + if ((c->x86 == 6) && (c->x86_model >= 0x0f)) { + if (!cpu_has_xstore_enabled) { + printk(KERN_ERR PFX "can't enable hardware RNG " + "if XSTORE is not enabled\n"); + return -ENODEV; + } + return 0; + } + /* Control the RNG via MSR. Tread lightly and pay very close * close attention to values written, as the reserved fields * are documented to be "undefined and unpredictable"; but it |