diff options
| author | Xiaolei Li | 2017-06-23 15:12:25 +0800 |
|---|---|---|
| committer | Boris Brezillon | 2017-06-25 16:54:01 +0200 |
| commit | 88404312556c10e4bcd1aeeb75b1b7e9e3226160 (patch) | |
| tree | a5651ff28ea231e694d0e651212bdbe08853914d /drivers | |
| parent | 188986c70e09f0f3cd88e6fe14c89e439474e3ec (diff) | |
mtd: nand: mtk: disable ecc irq when writing page with hwecc
Currently, ecc encode irq is enabled when writing page with hwecc, but
we actually do not wait for this irq done. Because NFI and ECC work in
parallel, nfi irq and ecc irq almost come together.
Now, there are two steps to check whether page data are totally written.
First, wait for nfi irq INTR_AHB_DONE. This is to ensure all data
in RAM are received by NFI.
Second, polling the register NFI_ADDRCNTR till all data include ecc
parity data runtime generated by ECC are sent to NAND device.
So, it is redunant to enable ecc irq without waiting for it.
Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/mtk_ecc.c | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/drivers/mtd/nand/mtk_ecc.c b/drivers/mtd/nand/mtk_ecc.c index a855a4e5cc35..00ce22e0eaf0 100644 --- a/drivers/mtd/nand/mtk_ecc.c +++ b/drivers/mtd/nand/mtk_ecc.c @@ -276,16 +276,18 @@ int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config) if (ret) return ret; - init_completion(&ecc->done); - reg_val = ECC_IRQ_EN; - /* - * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it - * means this chip can only generate one ecc irq during page - * read / write. If is 0, generate one ecc irq each ecc step. - */ - if ((ecc->caps->pg_irq_sel) && (config->mode == ECC_NFI_MODE)) - reg_val |= ECC_PG_IRQ_SEL; - writew(reg_val, ecc->regs + ECC_IRQ_REG(op)); + if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) { + init_completion(&ecc->done); + reg_val = ECC_IRQ_EN; + /* + * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it + * means this chip can only generate one ecc irq during page + * read / write. If is 0, generate one ecc irq each ecc step. + */ + if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE) + reg_val |= ECC_PG_IRQ_SEL; + writew(reg_val, ecc->regs + ECC_IRQ_REG(op)); + } writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); |