diff options
| author | Aapo Vienamo | 2018-08-10 21:14:01 +0300 |
|---|---|---|
| committer | Ulf Hansson | 2018-10-08 11:40:43 +0200 |
| commit | bc5568bf4c3f5f4f73e1c0263064ca038a136649 (patch) | |
| tree | b799e3d9d4d92e4920006a23a7f64d7d69888a54 /drivers | |
| parent | dfc9700cef771fbafd654c93327d930585b9e44c (diff) | |
mmc: tegra: Implement HS400 delay line calibration
Implement HS400 specific delay line calibration procedure. This is a
Tegra specific procedure and has to be performed regardless whether
enhanced strobe or HS400 tuning is used.
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a3f4452d6661..88ffc7e35d10 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -56,6 +56,12 @@ #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 +#define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0 +#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) + +#define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc +#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31) + #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 @@ -624,6 +630,24 @@ static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim) sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES); } +static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host) +{ + u32 reg; + int err; + + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); + reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; + sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); + + /* 1 ms sleep, 5 ms timeout */ + err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, + reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE), + 1000, 5000); + if (err) + dev_err(mmc_dev(host->mmc), + "HS400 delay line calibration timed out\n"); +} + static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { @@ -631,6 +655,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); bool set_default_tap = false; bool set_dqs_trim = false; + bool do_hs400_dll_cal = false; switch (timing) { case MMC_TIMING_UHS_SDR50: @@ -640,6 +665,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, break; case MMC_TIMING_MMC_HS400: set_dqs_trim = true; + do_hs400_dll_cal = true; break; case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: @@ -660,6 +686,9 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, if (set_dqs_trim) tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); + + if (do_hs400_dll_cal) + tegra_sdhci_hs400_dll_cal(host); } static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) |