diff options
| author | Vitaly Kuznetsov | 2021-03-23 09:45:15 +0100 |
|---|---|---|
| committer | Paolo Bonzini | 2021-03-30 13:07:10 -0400 |
| commit | 1973cadd4cca08eaeca944f60598f04ab0d80682 (patch) | |
| tree | bbac545a056e14aeabb38bef2c0145aa557f0c87 /fs/inode.c | |
| parent | ecaf088f53fcc893cd00c846f53042a536b9630d (diff) | |
KVM: x86/vPMU: Forbid writing to MSR_F15H_PERF MSRs when guest doesn't have X86_FEATURE_PERFCTR_CORE
MSR_F15H_PERF_CTL0-5, MSR_F15H_PERF_CTR0-5 MSRs are only available when
X86_FEATURE_PERFCTR_CORE CPUID bit was exposed to the guest. KVM, however,
allows these MSRs unconditionally because kvm_pmu_is_valid_msr() ->
amd_msr_idx_to_pmc() check always passes and because kvm_pmu_set_msr() ->
amd_pmu_set_msr() doesn't fail.
In case of a counter (CTRn), no big harm is done as we only increase
internal PMC's value but in case of an eventsel (CTLn), we go deep into
perf internals with a non-existing counter.
Note, kvm_get_msr_common() just returns '0' when these MSRs don't exist
and this also seems to contradict architectural behavior which is #GP
(I did check one old Opteron host) but changing this status quo is a bit
scarier.
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Message-Id: <20210323084515.1346540-1-vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'fs/inode.c')
0 files changed, 0 insertions, 0 deletions