diff options
| author | Alison Schofield | 2022-10-27 19:56:50 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki | 2022-10-28 17:28:23 +0200 |
| commit | f350c68e3cd5ce605e44c7830029cd936a223f66 (patch) | |
| tree | 65a50adf7ed8caae31ebc459b1a8b3b584dc9c08 /include/acpi | |
| parent | 183f0a09d32cf4f007f52718becf1b963549cb54 (diff) | |
ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table
ACPICA commit 2d8dc0383d3c908389053afbdc329bbd52f009ce
The CXL 3.0 Specification [1] adds two new structures to
the CXL Early Discovery Table (CEDT). The CEDT may include
zero or more entries of these types:
CXIMS: CXL XOR Interleave Math Structure
Enables the host to find a targets position in an
Interleave Target List when XOR Math is used.
RDPAS: RCEC Downstream Post Association Structure
Enables the host to locate the Downstream Port(s)
that report errors to a given Root Complex Event
Collector (RCEC).
Link: https://www.computeexpresslink.org/spec-landing # [1]
Link: https://github.com/acpica/acpica/commit/2d8dc038
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include/acpi')
| -rw-r--r-- | include/acpi/actbl1.h | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 15c78678c5d3..2aba6f516e70 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -329,7 +329,9 @@ struct acpi_cedt_header { enum acpi_cedt_type { ACPI_CEDT_TYPE_CHBS = 0, ACPI_CEDT_TYPE_CFMWS = 1, - ACPI_CEDT_TYPE_RESERVED = 2, + ACPI_CEDT_TYPE_CXIMS = 2, + ACPI_CEDT_TYPE_RDPAS = 3, + ACPI_CEDT_TYPE_RESERVED = 4, }; /* Values for version field above */ @@ -380,6 +382,7 @@ struct acpi_cedt_cfmws_target_element { /* Values for Interleave Arithmetic field above */ #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO (0) +#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR (1) /* Values for Restrictions field above */ @@ -389,6 +392,36 @@ struct acpi_cedt_cfmws_target_element { #define ACPI_CEDT_CFMWS_RESTRICT_PMEM (1<<3) #define ACPI_CEDT_CFMWS_RESTRICT_FIXED (1<<4) +/* 2: CXL XOR Interleave Math Structure */ + +struct acpi_cedt_cxims { + struct acpi_cedt_header header; + u16 reserved1; + u8 hbig; + u8 nr_xormaps; + u64 xormap_list[]; +}; + +/* 3: CXL RCEC Downstream Port Association Structure */ + +struct acpi_cedt_rdpas { + struct acpi_cedt_header header; + u8 reserved1; + u16 length; + u16 segment; + u16 bdf; + u8 protocol; + u64 address; +}; + +/* Masks for bdf field above */ +#define ACPI_CEDT_RDPAS_BUS_MASK 0xff00 +#define ACPI_CEDT_RDPAS_DEVICE_MASK 0x00f8 +#define ACPI_CEDT_RDPAS_FUNCTION_MASK 0x0007 + +#define ACPI_CEDT_RDPAS_PROTOCOL_IO (0) +#define ACPI_CEDT_RDPAS_PROTOCOL_CACHEMEM (1) + /******************************************************************************* * * CPEP - Corrected Platform Error Polling table (ACPI 4.0) |