diff options
| author | Steve French | 2005-11-09 14:33:22 -0800 |
|---|---|---|
| committer | Steve French | 2005-11-09 14:33:22 -0800 |
| commit | e82b3aec8d508d2a925a4c766e97f16b7c4dfb1b (patch) | |
| tree | 69d5685ef0c194f651a03e30bff14628b4d45400 /include/asm-arm | |
| parent | ec58ef03284f0bfa50a04982b74c8c2325a0758e (diff) | |
| parent | ad8f76be48d817b48222411ae16a7dfe257bdb24 (diff) | |
Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Diffstat (limited to 'include/asm-arm')
24 files changed, 492 insertions, 243 deletions
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h index f864c367c934..1386871e1a5a 100644 --- a/include/asm-arm/arch-clps711x/hardware.h +++ b/include/asm-arm/arch-clps711x/hardware.h @@ -235,121 +235,4 @@ #define CEIVA_PB0_BLK_BTN (1<<0) #endif // #if defined (CONFIG_ARCH_CEIVA) -#if defined (CONFIG_MACH_MP1000) -/* NOR FLASH */ -#define MP1000_NIO_BASE 0xf9000000 /* virtual */ -#define MP1000_NIO_START CS0_PHYS_BASE /* physical */ -#define MP1000_NIO_SIZE 0x00400000 - -/* DSP Interface */ -#define MP1000_DSP_BASE 0xfa000000 /* virtual */ -#define MP1000_DSP_START CS1_PHYS_BASE /* physical */ -#define MP1000_DSP_SIZE 0x00100000 - -/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */ -#define MP1000_LIO_BASE 0xfb000000 /* virtual */ -#define MP1000_LIO_START CS2_PHYS_BASE /* physical */ -#define MP1000_LIO_SIZE 0x00100000 - -/* NAND FLASH */ -#define MP1000_FIO_BASE 0xfc000000 /* virtual */ -#define MP1000_FIO_START CS3_PHYS_BASE /* physical */ -#define MP1000_FIO_SIZE 0x00800000 - -/* Ethernet */ -#define MP1000_EIO_BASE 0xfd000000 /* virtual */ -#define MP1000_EIO_START CS4_PHYS_BASE /* physical */ -#define MP1000_EIO_SIZE 0x00100000 - -#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */ -#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/ -#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */ -#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */ - -/* IDE */ -#define MP1000_IDE_BASE 0xfe000000 /* virtual */ -#define MP1000_IDE_START CS5_PHYS_BASE /* physical */ -#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */ - -#define IRQ_HARDDISK IRQ_EINT2 - -/* - * IDE registers definition - */ - -#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000) -#define IDE_BASE_OFF (MP1000_IDE_BASE) - -#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0) -#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2) -#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4) -#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6) -#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8) -#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa) -#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc) -#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe) -#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc) - -#define IDE_IRQ IRQ_EINT2 - - -#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2)) -#define RTC_ALWAYS_BCD 0 - -/* -// Definitions of the bit fields in the HwPortA register for the -// MP1000 board. -*/ -#define HwPortAKeyboardRow1 0x00000001 -#define HwPortAKeyboardRow2 0x00000002 -#define HwPortAKeyboardRow3 0x00000004 -#define HwPortAKeyboardRow4 0x00000008 -#define HwPortAKeyboardRow5 0x00000010 -#define HwPortAKeyboardRow6 0x00000020 -#define HwPortALCDEnable 0x00000040 -#define HwPortAOffhook 0x00000080 - -/* -// Definitions of the bit fields in the HwPortB register for the -// MP1000 board. -*/ -#define HwPortBL3Mode 0x00000001 -#define HwPortBL3Clk 0x00000002 -#define HwPortBSClk 0x00000001 -#define HwPortBSData 0x00000002 -#define HwPortBL3Data 0x00000004 -#define HwPortBMute 0x00000008 -#define HwPortBQD0 0x00000010 -#define HwPortBQD1 0x00000020 -#define HwPortBQD2 0x00000040 -#define HwPortBQD3 0x00000080 - -/* -// Definitions of the bit fields in the HwPortD register for the -// MP1000 board. -*/ -#define HwPortDLED1 0x00000001 -#define HwPortDLED2 0x00000002 -#define HwPortDLED3 0x00000004 -#define HwPortDLED4 0x00000008 -#define HwPortDLED5 0x00000010 -#define HwPortDEECS 0x00000020 -#define HwPortBRTS 0x00000040 -#define HwPortBRI 0x00000080 - - -/* -// Definitions of the bit fields in the HwPortE register for the -// MP1000 board. -*/ - -#define HwPortECLE 0x00000001 -#define HwPortESepromDOut 0x00000001 -#define HwPortEALE 0x00000002 -#define HwPortESepromDIn 0x00000002 -#define HwPortENANDCS 0x00000004 -#define HwPortESepromCLK 0x00000004 - -#endif // #if defined (CONFIG_MACH_MP1000) - #endif diff --git a/include/asm-arm/arch-clps711x/mp1000-seprom.h b/include/asm-arm/arch-clps711x/mp1000-seprom.h deleted file mode 100644 index 3e5566cf9666..000000000000 --- a/include/asm-arm/arch-clps711x/mp1000-seprom.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef MP1000_SEPROM_H -#define MP1000_SEPROM_H - -/* - * mp1000-seprom.h - * - * - * This file contains the Serial EEPROM definitions for the MP1000 board - * - * Copyright (C) 2005 Comdial Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#define COMMAND_ERASE (0x1C0) -#define COMMAND_ERASE_ALL (0x120) -#define COMMAND_WRITE_DISABLE (0x100) -#define COMMAND_WRITE_ENABLE (0x130) -#define COMMAND_READ (0x180) -#define COMMAND_WRITE (0x140) -#define COMMAND_WRITE_ALL (0x110) - -// -// Serial EEPROM data format -// - -#define PACKED __attribute__ ((packed)) - -typedef struct _EEPROM { - union { - unsigned char eprom_byte_data[128]; - unsigned short eprom_short_data[64]; - struct { - unsigned char version PACKED; // EEPROM Version "1" for now - unsigned char box_id PACKED; // Box ID (Standalone, SOHO, embedded, etc) - unsigned char major_hw_version PACKED; // Major Hardware version (Hex) - unsigned char minor_hw_version PACKED; // Minor Hardware Version (Hex) - unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic) - unsigned char mfg_serial_number[10] PACKED; // Manufacturer Serial number - unsigned char mfg_date[3] PACKED; // Date of Mfg (Formatted YY:MM:DD) - unsigned char country PACKED; // Country of deployment - unsigned char mac_Address[6] PACKED; // MAC Address - unsigned char oem_string[20] PACKED; // OEM ID string - unsigned short feature_bits1 PACKED; // Feature Bits 1 - unsigned short feature_bits2 PACKED; // Feature Bits 2 - unsigned char filler[75] PACKED; // Unused/Undefined “0” initialized - unsigned short checksum PACKED; // byte accumulated short checksum - } eprom_struct; - } variant; -} eeprom_struct; - -/* These settings must be mutually exclusive */ -#define FEATURE_BITS1_DRAMSIZE_16MEG 0x0001 /* 0 signifies 4 MEG system */ -#define FEATURE_BITS1_DRAMSIZE_8MEG 0x0002 /* 1 in bit 1 = 8MEG system */ -#define FEATURE_BITS1_DRAMSIZE_64MEG 0x0004 /* 1 in bit 2 = 64MEG system */ - -#define FEATURE_BITS1_CPUIS90MEG 0x0010 - -extern void seprom_init(void); -extern eeprom_struct* get_seprom_ptr(void); -extern unsigned char* get_eeprom_mac_address(void); - -#endif /* MP1000_SEPROM_H */ - diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h index 200621ff3690..f8df778a356f 100644 --- a/include/asm-arm/arch-iop3xx/iop321.h +++ b/include/asm-arm/arch-iop3xx/iop321.h @@ -40,7 +40,7 @@ #define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1) #define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA) -//#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) +/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */ #define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ #define IOP321_PCI_LOWER_MEM_PA 0x80000000 #define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0) diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h index 96adffd8bad2..fbf0cc11bdd9 100644 --- a/include/asm-arm/arch-iop3xx/iop331.h +++ b/include/asm-arm/arch-iop3xx/iop331.h @@ -42,7 +42,7 @@ /* this can be 128M if OMWTVR1 is set */ #define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */ -//#define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) +/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */ #define IOP331_PCI_LOWER_MEM_PA 0x80000000 #define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0) #define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1) diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h index 0deb96c12adb..62f09c7ff420 100644 --- a/include/asm-arm/arch-ixp2000/irqs.h +++ b/include/asm-arm/arch-ixp2000/irqs.h @@ -67,12 +67,45 @@ #define IRQ_IXP2000_PCIA 40 #define IRQ_IXP2000_PCIB 41 -#define NR_IXP2000_IRQS 42 +/* Int sources from IRQ_ERROR_STATUS */ +#define IRQ_IXP2000_DRAM0_MIN_ERR 42 +#define IRQ_IXP2000_DRAM0_MAJ_ERR 43 +#define IRQ_IXP2000_DRAM1_MIN_ERR 44 +#define IRQ_IXP2000_DRAM1_MAJ_ERR 45 +#define IRQ_IXP2000_DRAM2_MIN_ERR 46 +#define IRQ_IXP2000_DRAM2_MAJ_ERR 47 +/* 48-57 reserved */ +#define IRQ_IXP2000_SRAM0_ERR 58 +#define IRQ_IXP2000_SRAM1_ERR 59 +#define IRQ_IXP2000_SRAM2_ERR 60 +#define IRQ_IXP2000_SRAM3_ERR 61 +/* 62-65 reserved */ +#define IRQ_IXP2000_MEDIA_ERR 66 +#define IRQ_IXP2000_PCI_ERR 67 +#define IRQ_IXP2000_SP_INT 68 + +#define NR_IXP2000_IRQS 69 #define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x)) #define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS)) +#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) +#define IXP2000_VALID_ERR_IRQ_MASK (\ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) ) + /* * This allows for all the on-chip sources plus up to 32 CPLD based * IRQs. Should be more than enough. diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index 80d05ecad2f0..688f7f90d93e 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h @@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr) #define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x) #define __arch_iounmap(a) __ixp4xx_iounmap(a) -#define writeb(p, v) __ixp4xx_writeb(p, v) -#define writew(p, v) __ixp4xx_writew(p, v) -#define writel(p, v) __ixp4xx_writel(p, v) +#define writeb(v, p) __ixp4xx_writeb(v, p) +#define writew(v, p) __ixp4xx_writew(v, p) +#define writel(v, p) __ixp4xx_writel(v, p) #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) @@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr) #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) static inline void -__ixp4xx_writeb(u8 value, u32 addr) +__ixp4xx_writeb(u8 value, volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) { @@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr) } static inline void -__ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count) +__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) { while (count--) writeb(*vaddr++, bus_addr); } static inline void -__ixp4xx_writew(u16 value, u32 addr) +__ixp4xx_writew(u16 value, volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) { @@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr) } static inline void -__ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count) +__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) { while (count--) writew(*vaddr++, bus_addr); } static inline void -__ixp4xx_writel(u32 value, u32 addr) +__ixp4xx_writel(u32 value, volatile void __iomem *p) { + u32 addr = (u32)p; if (addr >= VMALLOC_START) { __raw_writel(value, addr); return; @@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr) } static inline void -__ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count) +__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) { while (count--) writel(*vaddr++, bus_addr); } static inline unsigned char -__ixp4xx_readb(u32 addr) +__ixp4xx_readb(const volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) @@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr) } static inline void -__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count) +__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) { while (count--) *vaddr++ = readb(bus_addr); } static inline unsigned short -__ixp4xx_readw(u32 addr) +__ixp4xx_readw(const volatile void __iomem *p) { + u32 addr = (u32)p; u32 n, byte_enables, data; if (addr >= VMALLOC_START) @@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr) } static inline void -__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count) +__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) { while (count--) *vaddr++ = readw(bus_addr); } static inline unsigned long -__ixp4xx_readl(u32 addr) +__ixp4xx_readl(const volatile void __iomem *p) { + u32 addr = (u32)p; u32 data; if (addr >= VMALLOC_START) @@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr) } static inline void -__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) +__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) { while (count--) *vaddr++ = readl(bus_addr); @@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) eth_copy_and_sum((s),__mem_pci(c),(l),(b)) static inline int -check_signature(unsigned long bus_addr, const unsigned char *signature, +check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature, int length) { int retval = 0; @@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) static inline unsigned int -__ixp4xx_ioread8(void __iomem *addr) +__ixp4xx_ioread8(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return (unsigned int)__raw_readb(port); #else - return (unsigned int)__ixp4xx_readb(port); + return (unsigned int)__ixp4xx_readb(addr); #endif } static inline void -__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) +__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsb(addr, vaddr, count); #else - __ixp4xx_readsb(port, vaddr, count); + __ixp4xx_readsb(addr, vaddr, count); #endif } static inline unsigned int -__ixp4xx_ioread16(void __iomem *addr) +__ixp4xx_ioread16(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le16_to_cpu(__raw_readw((u32)port)); #else - return (unsigned int)__ixp4xx_readw((u32)port); + return (unsigned int)__ixp4xx_readw(addr); #endif } static inline void -__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) +__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsw(addr, vaddr, count); #else - __ixp4xx_readsw(port, vaddr, count); + __ixp4xx_readsw(addr, vaddr, count); #endif } static inline unsigned int -__ixp4xx_ioread32(void __iomem *addr) +__ixp4xx_ioread32(const void __iomem *addr) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI return le32_to_cpu(__raw_readl((u32)port)); #else - return (unsigned int)__ixp4xx_readl((u32)port); + return (unsigned int)__ixp4xx_readl(addr); #endif } } static inline void -__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) +__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) { unsigned long port = (unsigned long __force)addr; if (__is_io_address(port)) @@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_readsl(addr, vaddr, count); #else - __ixp4xx_readsl(port, vaddr, count); + __ixp4xx_readsl(addr, vaddr, count); #endif } @@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writeb(value, port); #else - __ixp4xx_writeb(value, port); + __ixp4xx_writeb(value, addr); #endif } @@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesb(addr, vaddr, count); #else - __ixp4xx_writesb(port, vaddr, count); + __ixp4xx_writesb(addr, vaddr, count); #endif } @@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writew(cpu_to_le16(value), addr); #else - __ixp4xx_writew(value, port); + __ixp4xx_writew(value, addr); #endif } @@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesw(addr, vaddr, count); #else - __ixp4xx_writesw(port, vaddr, count); + __ixp4xx_writesw(addr, vaddr, count); #endif } @@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writel(cpu_to_le32(value), port); #else - __ixp4xx_writel(value, port); + __ixp4xx_writel(value, addr); #endif } @@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) #ifndef CONFIG_IXP4XX_INDIRECT_PCI __raw_writesl(addr, vaddr, count); #else - __ixp4xx_writesl(port, vaddr, count); + __ixp4xx_writesl(addr, vaddr, count); #endif } diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h new file mode 100644 index 000000000000..7a8a1cdf430d --- /dev/null +++ b/include/asm-arm/arch-pxa/pm.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +extern int pxa_pm_prepare(suspend_state_t state); +extern int pxa_pm_enter(suspend_state_t state); +extern int pxa_pm_finish(suspend_state_t state); diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h new file mode 100644 index 000000000000..c3364a2c4758 --- /dev/null +++ b/include/asm-arm/arch-pxa/tosa.h @@ -0,0 +1,166 @@ +/* + * Hardware specific definitions for Sharp SL-C6000x series of PDAs + * + * Copyright (c) 2005 Dirk Opfer + * + * Based on Sharp's 2.4 kernel patches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ +#ifndef _ASM_ARCH_TOSA_H_ +#define _ASM_ARCH_TOSA_H_ 1 + +/* TOSA Chip selects */ +#define TOSA_LCDC_PHYS PXA_CS4_PHYS +/* Internel Scoop */ +#define TOSA_CF_PHYS (PXA_CS2_PHYS + 0x00800000) +/* Jacket Scoop */ +#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) + +/* + * SCOOP2 internal GPIOs + */ +#define TOSA_SCOOP_PXA_VCORE1 SCOOP_GPCR_PA11 +#define TOSA_SCOOP_TC6393_REST_IN SCOOP_GPCR_PA12 +#define TOSA_SCOOP_IR_POWERDWN SCOOP_GPCR_PA13 +#define TOSA_SCOOP_SD_WP SCOOP_GPCR_PA14 +#define TOSA_SCOOP_PWR_ON SCOOP_GPCR_PA15 +#define TOSA_SCOOP_AUD_PWR_ON SCOOP_GPCR_PA16 +#define TOSA_SCOOP_BT_RESET SCOOP_GPCR_PA17 +#define TOSA_SCOOP_BT_PWR_EN SCOOP_GPCR_PA18 +#define TOSA_SCOOP_AC_IN_OL SCOOP_GPCR_PA19 + +/* GPIO Direction 1 : output mode / 0:input mode */ +#define TOSA_SCOOP_IO_DIR ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \ + TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\ + TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN ) +/* GPIO out put level when init 1: Hi */ +#define TOSA_SCOOP_IO_OUT ( TOSA_SCOOP_TC6393_REST_IN ) + +/* + * SCOOP2 jacket GPIOs + */ +#define TOSA_SCOOP_JC_BT_LED SCOOP_GPCR_PA11 +#define TOSA_SCOOP_JC_NOTE_LED SCOOP_GPCR_PA12 +#define TOSA_SCOOP_JC_CHRG_ERR_LED SCOOP_GPCR_PA13 +#define TOSA_SCOOP_JC_USB_PULLUP SCOOP_GPCR_PA14 +#define TOSA_SCOOP_JC_TC6393_SUSPEND SCOOP_GPCR_PA15 +#define TOSA_SCOOP_JC_TC3693_L3V_ON SCOOP_GPCR_PA16 +#define TOSA_SCOOP_JC_WLAN_DETECT SCOOP_GPCR_PA17 +#define TOSA_SCOOP_JC_WLAN_LED SCOOP_GPCR_PA18 +#define TOSA_SCOOP_JC_CARD_LIMIT_SEL SCOOP_GPCR_PA19 + +/* GPIO Direction 1 : output mode / 0:input mode */ +#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \ + TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \ + TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \ + TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL ) +/* GPIO out put level when init 1: Hi */ +#define TOSA_SCOOP_JC_IO_OUT ( 0 ) + +/* + * Timing Generator + */ +#define TG_PNLCTL 0x00 +#define TG_TPOSCTL 0x01 +#define TG_DUTYCTL 0x02 +#define TG_GPOSR 0x03 +#define TG_GPODR1 0x04 +#define TG_GPODR2 0x05 +#define TG_PINICTL 0x06 +#define TG_HPOSCTL 0x07 + +/* + * LED + */ +#define TOSA_SCOOP_LED_BLUE TOSA_SCOOP_GPCR_PA11 +#define TOSA_SCOOP_LED_GREEN TOSA_SCOOP_GPCR_PA12 +#define TOSA_SCOOP_LED_ORANGE TOSA_SCOOP_GPCR_PA13 +#define TOSA_SCOOP_LED_WLAN TOSA_SCOOP_GPCR_PA18 + + +/* + * PXA GPIOs + */ +#define TOSA_GPIO_POWERON (0) +#define TOSA_GPIO_RESET (1) +#define TOSA_GPIO_AC_IN (2) +#define TOSA_GPIO_RECORD_BTN (3) +#define TOSA_GPIO_SYNC (4) /* Cradle SYNC Button */ +#define TOSA_GPIO_USB_IN (5) +#define TOSA_GPIO_JACKET_DETECT (7) +#define TOSA_GPIO_nSD_DETECT (9) +#define TOSA_GPIO_nSD_INT (10) +#define TOSA_GPIO_TC6393_CLK (11) +#define TOSA_GPIO_BAT1_CRG (12) +#define TOSA_GPIO_CF_CD (13) +#define TOSA_GPIO_BAT0_CRG (14) +#define TOSA_GPIO_TC6393_INT (15) +#define TOSA_GPIO_BAT0_LOW (17) +#define TOSA_GPIO_TC6393_RDY (18) +#define TOSA_GPIO_ON_RESET (19) +#define TOSA_GPIO_EAR_IN (20) +#define TOSA_GPIO_CF_IRQ (21) /* CF slot0 Ready */ +#define TOSA_GPIO_ON_KEY (22) +#define TOSA_GPIO_VGA_LINE (27) +#define TOSA_GPIO_TP_INT (32) /* Touch Panel pen down interrupt */ +#define TOSA_GPIO_JC_CF_IRQ (36) /* CF slot1 Ready */ +#define TOSA_GPIO_BAT_LOCKED (38) /* Battery locked */ +#define TOSA_GPIO_TG_SPI_SCLK (81) +#define TOSA_GPIO_TG_SPI_CS (82) +#define TOSA_GPIO_TG_SPI_MOSI (83) +#define TOSA_GPIO_BAT1_LOW (84) + +#define TOSA_GPIO_HP_IN GPIO_EAR_IN + +#define TOSA_GPIO_MAIN_BAT_LOW GPIO_BAT0_LOW + +#define TOSA_KEY_STROBE_NUM (11) +#define TOSA_KEY_SENSE_NUM (7) + +#define TOSA_GPIO_HIGH_STROBE_BIT (0xfc000000) +#define TOSA_GPIO_LOW_STROBE_BIT (0x0000001f) +#define TOSA_GPIO_ALL_SENSE_BIT (0x00000fe0) +#define TOSA_GPIO_ALL_SENSE_RSHIFT (5) +#define TOSA_GPIO_STROBE_BIT(a) GPIO_bit(58+(a)) +#define TOSA_GPIO_SENSE_BIT(a) GPIO_bit(69+(a)) +#define TOSA_GAFR_HIGH_STROBE_BIT (0xfff00000) +#define TOSA_GAFR_LOW_STROBE_BIT (0x000003ff) +#define TOSA_GAFR_ALL_SENSE_BIT (0x00fffc00) +#define TOSA_GPIO_KEY_SENSE(a) (69+(a)) +#define TOSA_GPIO_KEY_STROBE(a) (58+(a)) + +/* + * Interrupts + */ +#define TOSA_IRQ_GPIO_WAKEUP IRQ_GPIO(TOSA_GPIO_WAKEUP) +#define TOSA_IRQ_GPIO_AC_IN IRQ_GPIO(TOSA_GPIO_AC_IN) +#define TOSA_IRQ_GPIO_RECORD_BTN IRQ_GPIO(TOSA_GPIO_RECORD_BTN) +#define TOSA_IRQ_GPIO_SYNC IRQ_GPIO(TOSA_GPIO_SYNC) +#define TOSA_IRQ_GPIO_USB_IN IRQ_GPIO(TOSA_GPIO_USB_IN) +#define TOSA_IRQ_GPIO_JACKET_DETECT IRQ_GPIO(TOSA_GPIO_JACKET_DETECT) +#define TOSA_IRQ_GPIO_nSD_INT IRQ_GPIO(TOSA_GPIO_nSD_INT) +#define TOSA_IRQ_GPIO_nSD_DETECT IRQ_GPIO(TOSA_GPIO_nSD_DETECT) +#define TOSA_IRQ_GPIO_BAT1_CRG IRQ_GPIO(TOSA_GPIO_BAT1_CRG) +#define TOSA_IRQ_GPIO_CF_CD IRQ_GPIO(TOSA_GPIO_CF_CD) +#define TOSA_IRQ_GPIO_BAT0_CRG IRQ_GPIO(TOSA_GPIO_BAT0_CRG) +#define TOSA_IRQ_GPIO_TC6393_INT IRQ_GPIO(TOSA_GPIO_TC6393_INT) +#define TOSA_IRQ_GPIO_BAT0_LOW IRQ_GPIO(TOSA_GPIO_BAT0_LOW) +#define TOSA_IRQ_GPIO_EAR_IN IRQ_GPIO(TOSA_GPIO_EAR_IN) +#define TOSA_IRQ_GPIO_CF_IRQ IRQ_GPIO(TOSA_GPIO_CF_IRQ) +#define TOSA_IRQ_GPIO_ON_KEY IRQ_GPIO(TOSA_GPIO_ON_KEY) +#define TOSA_IRQ_GPIO_VGA_LINE IRQ_GPIO(TOSA_GPIO_VGA_LINE) +#define TOSA_IRQ_GPIO_TP_INT IRQ_GPIO(TOSA_GPIO_TP_INT) +#define TOSA_IRQ_GPIO_JC_CF_IRQ IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ) +#define TOSA_IRQ_GPIO_BAT_LOCKED IRQ_GPIO(TOSA_GPIO_BAT_LOCKED) +#define TOSA_IRQ_GPIO_BAT1_LOW IRQ_GPIO(TOSA_GPIO_BAT1_LOW) +#define TOSA_IRQ_GPIO_KEY_SENSE(a) IRQ_GPIO(69+(a)) + +#define TOSA_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW) + +extern struct platform_device tosascoop_jc_device; +extern struct platform_device tosascoop_device; +#endif /* _ASM_ARCH_TOSA_H_ */ diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S index 2712ba77bb3a..6288fad0dc41 100644 --- a/include/asm-arm/arch-realview/entry-macro.S +++ b/include/asm-arm/arch-realview/entry-macro.S @@ -47,3 +47,28 @@ cmpcs \irqnr, \irqnr .endm + + /* We assume that irqstat (the raw value of the IRQ acknowledge + * register) is preserved from the macro above. + * If there is an IPI, we immediately signal end of interrupt on the + * controller, since this requires the original irqstat value which + * we won't easily be able to recreate later. + */ + + .macro test_for_ipi, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + cmp \irqnr, #16 + strcc \irqstat, [\base, #GIC_CPU_EOI] + cmpcs \irqnr, \irqnr + .endm + + /* As above, this assumes that irqstat and base are preserved.. */ + + .macro test_for_ltirq, irqnr, irqstat, base, tmp + bic \irqnr, \irqstat, #0x1c00 + mov \tmp, #0 + cmp \irqnr, #29 + moveq \tmp, #1 + streq \irqstat, [\base, #GIC_CPU_EOI] + cmp \tmp, #0 + .endm diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index ff376494e5b1..c16223c9588d 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h @@ -21,6 +21,9 @@ #include <asm/arch/platform.h> +#define IRQ_LOCALTIMER 29 +#define IRQ_LOCALWDOG 30 + /* * IRQ interrupts definitions are the same the INT definitions * held within platform.h diff --git a/include/asm-arm/arch-realview/memory.h b/include/asm-arm/arch-realview/memory.h index 99667d5cc617..ed370abb638f 100644 --- a/include/asm-arm/arch-realview/memory.h +++ b/include/asm-arm/arch-realview/memory.h @@ -23,7 +23,7 @@ /* * Physical DRAM offset. */ -#define PHYS_OFFSET (0x00000000UL) +#define PHYS_OFFSET UL(0x00000000) /* * Virtual view <-> DMA view memory address translations diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h index 4b6de13a6b9a..18d7c18b738c 100644 --- a/include/asm-arm/arch-realview/platform.h +++ b/include/asm-arm/arch-realview/platform.h @@ -203,8 +203,16 @@ /* Reserved 0x1001A000 - 0x1001FFFF */ #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ #define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ +#ifndef CONFIG_REALVIEW_MPCORE #define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ #define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ +#else +#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */ +#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */ +#define REALVIEW_TWD_BASE 0x10100700 +#define REALVIEW_TWD_SIZE 0x00000100 +#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */ +#endif #define REALVIEW_SMC_BASE 0x10080000 /* SMC */ /* Reserved 0x10090000 - 0x100EFFFF */ @@ -265,6 +273,7 @@ * Interrupts - bit assignment (primary) * ------------------------------------------------------------------------ */ +#ifndef CONFIG_REALVIEW_MPCORE #define INT_WDOGINT 0 /* Watchdog timer */ #define INT_SOFTINT 1 /* Software interrupt */ #define INT_COMMRx 2 /* Debug Comm Rx interrupt */ @@ -297,6 +306,52 @@ #define INT_USB 29 /* USB controller */ #define INT_TSPENINT 30 /* Touchscreen pen */ #define INT_TSKPADINT 31 /* Touchscreen keypad */ +#else +#define INT_AACI 0 +#define INT_TIMERINT0_1 1 +#define INT_TIMERINT2_3 2 +#define INT_USB 3 +#define INT_UARTINT0 4 +#define INT_UARTINT1 5 +#define INT_RTCINT 6 +#define INT_KMI0 7 +#define INT_KMI1 8 +#define INT_ETH 9 +#define INT_EB_IRQ1 10 /* main GIC */ +#define INT_EB_IRQ2 11 /* tile GIC */ +#define INT_EB_FIQ1 12 /* main GIC */ +#define INT_EB_FIQ2 13 /* tile GIC */ +#define INT_MMCI0A 14 +#define INT_MMCI0B 15 + +#define INT_PMU_CPU0 17 +#define INT_PMU_CPU1 18 +#define INT_PMU_CPU2 19 +#define INT_PMU_CPU3 20 +#define INT_PMU_SCU0 21 +#define INT_PMU_SCU1 22 +#define INT_PMU_SCU2 23 +#define INT_PMU_SCU3 24 +#define INT_PMU_SCU4 25 +#define INT_PMU_SCU5 26 +#define INT_PMU_SCU6 27 +#define INT_PMU_SCU7 28 + +#define INT_L220_EVENT 29 +#define INT_L220_SLAVE 30 +#define INT_L220_DECODE 31 + +#define INT_UARTINT2 -1 +#define INT_UARTINT3 -1 +#define INT_CLCDINT -1 +#define INT_DMAINT -1 +#define INT_WDOGINT -1 +#define INT_GPIOINT0 -1 +#define INT_GPIOINT1 -1 +#define INT_GPIOINT2 -1 +#define INT_SCIINT -1 +#define INT_SSPINT -1 +#endif /* * Interrupt bit positions diff --git a/include/asm-arm/arch-realview/smp.h b/include/asm-arm/arch-realview/smp.h new file mode 100644 index 000000000000..fc87783e8e8b --- /dev/null +++ b/include/asm-arm/arch-realview/smp.h @@ -0,0 +1,31 @@ +#ifndef ASMARM_ARCH_SMP_H +#define ASMARM_ARCH_SMP_H + +#include <linux/config.h> + +#include <asm/hardware/gic.h> + +#define hard_smp_processor_id() \ + ({ \ + unsigned int cpunum; \ + __asm__("mrc p15, 0, %0, c0, c0, 5" \ + : "=r" (cpunum)); \ + cpunum &= 0x0F; \ + }) + +/* + * We use IRQ1 as the IPI + */ +static inline void smp_cross_call(cpumask_t callmap) +{ + gic_raise_softirq(callmap, 1); +} + +/* + * Do nothing on MPcore. + */ +static inline void smp_cross_call_done(cpumask_t callmap) +{ +} + +#endif diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h index d7a4a8354fa9..ddd1578a7ee0 100644 --- a/include/asm-arm/arch-s3c2410/uncompress.h +++ b/include/asm-arm/arch-s3c2410/uncompress.h @@ -116,6 +116,8 @@ putstr(const char *ptr) } } +#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) + /* CONFIG_S3C2410_BOOT_WATCHDOG * * Simple boot-time watchdog setup, to reboot the system if there is @@ -126,8 +128,6 @@ putstr(const char *ptr) #define WDOG_COUNT (0xff00) -#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) - static inline void arch_decomp_wdog(void) { __raw_writel(WDOG_COUNT, S3C2410_WTCNT); @@ -145,6 +145,24 @@ static void arch_decomp_wdog_start(void) #define arch_decomp_wdog() #endif +#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET + +static void arch_decomp_error(const char *x) +{ + putstr("\n\n"); + putstr(x); + putstr("\n\n -- System resetting\n"); + + __raw_writel(0x4000, S3C2410_WTDAT); + __raw_writel(0x4000, S3C2410_WTCNT); + __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); + + while(1); +} + +#define arch_error arch_decomp_error +#endif + static void error(char *err); static void diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index 69a28f96bee2..f31ac92b6c7f 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h @@ -83,10 +83,13 @@ * Save the current IRQ state and disable IRQs. Note that this macro * assumes FIQs are enabled, and that the processor is in SVC mode. */ - .macro save_and_disable_irqs, oldcpsr, temp + .macro save_and_disable_irqs, oldcpsr mrs \oldcpsr, cpsr - mov \temp, #PSR_I_BIT | MODE_SVC - msr cpsr_c, \temp +#if __LINUX_ARM_ARCH__ >= 6 + cpsid i +#else + msr cpsr_c, #PSR_I_BIT | MODE_SVC +#endif .endm /* diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h index fcbdd40cb667..751bc7462074 100644 --- a/include/asm-arm/cpu.h +++ b/include/asm-arm/cpu.h @@ -16,6 +16,7 @@ struct cpuinfo_arm { struct cpu cpu; #ifdef CONFIG_SMP + struct task_struct *idle; unsigned int loops_per_jiffy; #endif }; diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h index e5ccb6b8ff83..1cbb173bf5b1 100644 --- a/include/asm-arm/hardirq.h +++ b/include/asm-arm/hardirq.h @@ -8,6 +8,7 @@ typedef struct { unsigned int __softirq_pending; + unsigned int local_timer_irqs; } ____cacheline_aligned irq_cpustat_t; #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h new file mode 100644 index 000000000000..9903f60c84b7 --- /dev/null +++ b/include/asm-arm/hardware/arm_scu.h @@ -0,0 +1,13 @@ +#ifndef ASMARM_HARDWARE_ARM_SCU_H +#define ASMARM_HARDWARE_ARM_SCU_H + +/* + * SCU registers + */ +#define SCU_CTRL 0x00 +#define SCU_CONFIG 0x04 +#define SCU_CPU_STATUS 0x08 +#define SCU_INVALIDATE 0x0c +#define SCU_FPGA_REVISION 0x10 + +#endif diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h index a8f1013930e3..d37bf7443264 100644 --- a/include/asm-arm/hardware/scoop.h +++ b/include/asm-arm/hardware/scoop.h @@ -52,8 +52,14 @@ struct scoop_pcmcia_dev { unsigned char keep_rd; }; -extern int scoop_num; -extern struct scoop_pcmcia_dev *scoop_devs; +struct scoop_pcmcia_config { + struct scoop_pcmcia_dev *devs; + int num_devs; + void (*pcmcia_init)(void); + void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr); +}; + +extern struct scoop_pcmcia_config *platform_scoop_config; void reset_scoop(struct device *dev); unsigned short set_scoop_gpio(struct device *dev, unsigned short bit); diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h index f97912fbb10f..59975ee43cf1 100644 --- a/include/asm-arm/irq.h +++ b/include/asm-arm/irq.h @@ -47,5 +47,6 @@ struct irqaction; struct pt_regs; int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); +extern void migrate_irqs(void); #endif diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h index cd57436d9874..05b029ef6371 100644 --- a/include/asm-arm/mach/flash.h +++ b/include/asm-arm/mach/flash.h @@ -11,6 +11,7 @@ #define ASMARM_MACH_FLASH_H struct mtd_partition; +struct mtd_info; /* * map_name: the map probe function name @@ -19,6 +20,7 @@ struct mtd_partition; * init: method called at driver/device initialisation * exit: method called at driver/device removal * set_vpp: method called to enable or disable VPP + * mmcontrol: method called to enable or disable Sync. Burst Read in OneNAND * parts: optional array of mtd_partitions for static partitioning * nr_parts: number of mtd_partitions for static partitoning */ @@ -29,6 +31,7 @@ struct flash_platform_data { int (*init)(void); void (*exit)(void); void (*set_vpp)(int on); + void (*mmcontrol)(struct mtd_info *mtd, int sync_read); struct mtd_partition *parts; unsigned int nr_parts; }; diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 4af9c411c617..3d4b810d8c38 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARM_MMU_CONTEXT_H #define __ASM_ARM_MMU_CONTEXT_H +#include <asm/cacheflush.h> #include <asm/proc-fns.h> #if __LINUX_ARM_ARCH__ >= 6 @@ -86,7 +87,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, cpu_set(cpu, next->cpu_vm_mask); check_context(next); cpu_switch_mm(next->pgd, next); - cpu_clear(cpu, prev->cpu_vm_mask); + if (cache_is_vivt()) + cpu_clear(cpu, prev->cpu_vm_mask); } } diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h index dbb4d859c586..5a72e50ca9fc 100644 --- a/include/asm-arm/smp.h +++ b/include/asm-arm/smp.h @@ -37,6 +37,11 @@ struct seq_file; extern void show_ipi_list(struct seq_file *p); /* + * Called from assembly code, this handles an IPI. + */ +asmlinkage void do_IPI(struct pt_regs *regs); + +/* * Move global data into per-processor storage. */ extern void smp_store_cpu_info(unsigned int cpuid); @@ -47,12 +52,23 @@ extern void smp_store_cpu_info(unsigned int cpuid); extern void smp_cross_call(cpumask_t callmap); /* + * Broadcast a timer interrupt to the other CPUs. + */ +extern void smp_send_timer(void); + +/* * Boot a secondary CPU, and assign it the specified idle task. * This also gives us the initial stack to use for this CPU. */ extern int boot_secondary(unsigned int cpu, struct task_struct *); /* + * Called from platform specific assembly code, this is the + * secondary CPU entry point. + */ +asmlinkage void secondary_start_kernel(void); + +/* * Perform platform specific initialisation of the specified CPU. */ extern void platform_secondary_init(unsigned int cpu); @@ -66,4 +82,52 @@ struct secondary_data { }; extern struct secondary_data secondary_data; +extern int __cpu_disable(void); +extern int mach_cpu_disable(unsigned int cpu); + +extern void __cpu_die(unsigned int cpu); +extern void cpu_die(void); + +extern void platform_cpu_die(unsigned int cpu); +extern int platform_cpu_kill(unsigned int cpu); +extern void platform_cpu_enable(unsigned int cpu); + +#ifdef CONFIG_LOCAL_TIMERS +/* + * Setup a local timer interrupt for a CPU. + */ +extern void local_timer_setup(unsigned int cpu); + +/* + * Stop a local timer interrupt. + */ +extern void local_timer_stop(unsigned int cpu); + +/* + * Platform provides this to acknowledge a local timer IRQ + */ +extern int local_timer_ack(void); + +#else + +static inline void local_timer_setup(unsigned int cpu) +{ +} + +static inline void local_timer_stop(unsigned int cpu) +{ +} + +#endif + +/* + * show local interrupt info + */ +extern void show_local_irqs(struct seq_file *); + +/* + * Called from assembly, this is the local timer IRQ handler + */ +asmlinkage void do_local_timer(struct pt_regs *); + #endif /* ifndef __ASM_ARM_SMP_H */ diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h index cb4906b45555..6ed4f916b166 100644 --- a/include/asm-arm/spinlock.h +++ b/include/asm-arm/spinlock.h @@ -80,7 +80,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock) */ #define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0) -static inline void __raw_write_lock(rwlock_t *rw) +static inline void __raw_write_lock(raw_rwlock_t *rw) { unsigned long tmp; @@ -97,7 +97,7 @@ static inline void __raw_write_lock(rwlock_t *rw) smp_mb(); } -static inline int __raw_write_trylock(rwlock_t *rw) +static inline int __raw_write_trylock(raw_rwlock_t *rw) { unsigned long tmp; @@ -157,7 +157,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) smp_mb(); } -static inline void __raw_read_unlock(rwlock_t *rw) +static inline void __raw_read_unlock(raw_rwlock_t *rw) { unsigned long tmp, tmp2; |