diff options
| author | Ankit Nautiyal | 2021-03-23 16:54:21 +0530 |
|---|---|---|
| committer | Jani Nikula | 2021-03-31 12:21:06 +0300 |
| commit | 68a8c645b2538c1cbecf62de916d4f92f03978fb (patch) | |
| tree | daee97b6df9077be5cd979cf227102005e09d2e0 /include/drm | |
| parent | 25926cd856bea1e25f87f35c6fd935b4161b869b (diff) | |
drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
Currently the FRL training mode (Concurrent, Sequential) and
training type (Normal, Extended) are not defined properly and
are passed as bool values in drm_helpers for pcon
configuration for FRL training.
This patch:
-Add register masks for Sequential and Normal FRL training options.
-Fixes the drm_helpers for FRL Training configuration to use the
appropriate masks.
-Modifies the calls to the above drm_helpers in i915/intel_dp as per
the above change.
v2: Re-used the register masks for these options, instead of enum. (Ville)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210323112422.1211-2-ankit.k.nautiyal@intel.com
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/drm_dp_helper.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 632ad7faa006..85d728f4aad0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1176,6 +1176,7 @@ struct drm_device; # define DP_PCON_ENABLE_MAX_BW_48GBPS 6 # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) # define DP_PCON_ENABLE_HPD_READY (1 << 6) # define DP_PCON_ENABLE_HDMI_LINK (1 << 7) @@ -1190,6 +1191,7 @@ struct drm_device; # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) /* PCON HDMI LINK STATUS */ #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B @@ -2154,9 +2156,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode); + u8 frl_mode); int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode); + u8 frl_type); int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); |