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authorAdam Ford2020-06-03 10:43:28 -0500
committerStephen Boyd2020-06-22 19:04:58 -0700
commit34662f6e30846ae0f82bbc9605deff67781f6616 (patch)
tree1efcdc17e29bd2d129cd00b8ad694df82e44b438 /include/dt-bindings/clk
parentf491276a5168598758ea7fc381195e4ba9af39f8 (diff)
dt: Add additional option bindings for IDT VersaClock
The VersaClock driver now supports some additional bindings to support child nodes which can configure optional settings like mode, voltage and slew. This patch updates the binding document to describe what is available in the driver. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200603154329.31579-2-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings/clk')
-rw-r--r--include/dt-bindings/clk/versaclock.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h
new file mode 100644
index 000000000000..c6a6a0946564
--- /dev/null
+++ b/include/dt-bindings/clk/versaclock.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* This file defines field values used by the versaclock 6 family
+ * for defining output type
+ */
+
+#define VC5_LVPECL 0
+#define VC5_CMOS 1
+#define VC5_HCSL33 2
+#define VC5_LVDS 3
+#define VC5_CMOS2 4
+#define VC5_CMOSD 5
+#define VC5_HCSL25 6