diff options
| author | Linus Torvalds | 2021-09-07 13:52:46 -0700 |
|---|---|---|
| committer | Linus Torvalds | 2021-09-07 13:52:46 -0700 |
| commit | 4c00e1e2e58eefb288ba9ef585b6f19e1f33bf1e (patch) | |
| tree | a93c3263c4ea522eaf5b20de12a47f3dee04f92c /include/dt-bindings | |
| parent | 192ad3c27a4895ee4b2fa31c5b54a932f5bb08c1 (diff) | |
| parent | 41e73feb1024929e75eaf2f7cd93f35a3feb331b (diff) | |
Merge tag 'linux-watchdog-5.15-rc1' of git://www.linux-watchdog.org/linux-watchdog
Pull watchdog updates from Wim Van Sebroeck:
- add Mediatek MT7986 & MT8195 wdt support
- add Maxim MAX63xx
- drop bd70528 support
- rewrite ixp4xx to watchdog framework
- constify static struct watchdog_ops for sl28cpld_wdt, mpc8xxx_wdt and
tqmx86
- introduce watchdog_dev_suspend/resume
- several fixes and improvements
* tag 'linux-watchdog-5.15-rc1' of git://www.linux-watchdog.org/linux-watchdog:
dt-bindings: watchdog: Add compatible for Mediatek MT7986
watchdog: ixp4xx: Rewrite driver to use core
watchdog: Start watchdog in watchdog_set_last_hw_keepalive only if appropriate
watchdog: max63xx_wdt: Add device tree probing
dt-bindings: watchdog: Add Maxim MAX63xx bindings
watchdog: mediatek: mt8195: add wdt support
dt-bindings: reset: mt8195: add toprgu reset-controller header file
watchdog: tqmx86: Constify static struct watchdog_ops
watchdog: mpc8xxx_wdt: Constify static struct watchdog_ops
watchdog: sl28cpld_wdt: Constify static struct watchdog_ops
watchdog: iTCO_wdt: Fix detection of SMI-off case
watchdog: bcm2835_wdt: consider system-power-controller property
watchdog: imx2_wdg: notify wdog core to stop ping worker on suspend
watchdog: introduce watchdog_dev_suspend/resume
watchdog: Fix NULL pointer dereference when releasing cdev
watchdog: only run driver set_pretimeout op if device supports it
watchdog: bd70528 drop bd70528 support
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/reset/mt8195-resets.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h new file mode 100644 index 000000000000..a26bccc8b957 --- /dev/null +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Christine Zhu <christine.zhu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ |