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authorAlexandre Mergnat2024-04-18 16:17:00 +0200
committerStephen Boyd2024-04-19 18:53:35 -0700
commit4c0c087772d7e29bc2489ddb068d5167140bfc38 (patch)
tree473636ee6afc8539987fe11ee4f8ecfce33f37c6 /include/dt-bindings
parentbb7b3c8e7180f36de75cdea200ab7127f93f58cc (diff)
clk: mediatek: mt8365-mm: fix DPI0 parent
To have a working display through DPI, a workaround has been implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to the DPI node. Shortly, that add an extra clock. It seems consistent to have the "dpi0_sel" as parent. Additionnaly, "vpll_dpix" isn't used/managed. Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel". The new clock tree is: clk26m lvdspll lvdspll_X (2, 4, 8, 16) dpi0_sel mm_dpi0_dpi0 Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC") Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20231023-display-support-v3-12-53388f3ed34b@baylibre.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings')
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