diff options
| author | Vlad.Karpovich | 2023-03-15 10:47:18 -0500 |
|---|---|---|
| committer | Mark Brown | 2023-03-21 12:46:39 +0000 |
| commit | fa8c052b4c614aa1d2d60e5c9f40e9d885bf9511 (patch) | |
| tree | 468477082a18d0a77a36a5f2cfe1ddb603752834 /include/dt-bindings | |
| parent | 00a7ef3242f42c38c9ffdf14ab2d729fd9754391 (diff) | |
ASoC: cs35l45: Support for GPIO pins configuration.
Adds device tree configuration for cs35l45 GPIOs
Signed-off-by: Vlad Karpovich <vkarpovi@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230315154722.3911463-1-vkarpovi@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/sound/cs35l45.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/include/dt-bindings/sound/cs35l45.h b/include/dt-bindings/sound/cs35l45.h index 076da4b2c28d..25386af18445 100644 --- a/include/dt-bindings/sound/cs35l45.h +++ b/include/dt-bindings/sound/cs35l45.h @@ -17,4 +17,61 @@ #define CS35L45_ASP_TX_HIZ_UNUSED 0x1 #define CS35L45_ASP_TX_HIZ_DISABLED 0x2 +/* + * Optional GPIOX Sub-nodes: + * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3]) + * sub-nodes for configuring the GPIO pins. + * + * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl' + * is 1. + * 0 = Output + * 1 = Input (Default) + * + * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0. + * + * 0 = Low (Default) + * 1 = High + * + * - gpio-op-cfg : GPIO output configuration. Valid only when 'gpio-ctrl' is 1 + * and 'gpio-dir' is 0. + * + * 0 = CMOS (Default) + * 1 = Open Drain + * + * - gpio-pol : GPIO output polarity select. Valid only when 'gpio-ctrl' is 1 + * and 'gpio-dir' is 0. + * + * 0 = Non-inverted, Active High (Default) + * 1 = Inverted, Active Low + * + * - gpio-invert : Defines the polarity of the GPIO pin if configured + * as input. + * + * 0 = Not inverted (Default) + * 1 = Inverted + * + * - gpio-ctrl : Defines the function of the GPIO pin. + * + * GPIO1: + * 0 = High impedance input (Default) + * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir' + * 2 = Pin acts as MDSYNC, direction controlled by MDSYNC + * 3-7 = Reserved + * + * GPIO2: + * 0 = High impedance input (Default) + * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir' + * 2 = Pin acts as open drain INT + * 3 = Reserved + * 4 = Pin acts as push-pull output INT. Active low. + * 5 = Pin acts as push-pull output INT. Active high. + * 6,7 = Reserved + * + * GPIO3: + * 0 = High impedance input (Default) + * 1 = Pin acts as a GPIO, direction controlled by 'gpio-dir' + * 2-7 = Reserved + */ +#define CS35L45_NUM_GPIOS 0x3 + #endif /* DT_CS35L45_H */ |