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authorShaik Ameer Basha2014-05-08 16:57:51 +0530
committerTomasz Figa2014-05-14 19:40:17 +0200
commit3a767b35c6c2f2e5f75e22a429b4d6d8c6736626 (patch)
tree98517cb1751844910af47e5f9803c2d854ef95d4 /include/dt-bindings
parentdbd713bb907e83453b4811d585b96a4bc86df619 (diff)
clk: samsung: exynos5420: add clocks for ISP block
This patch adds minimum set of clocks to gate ISP block for power saving. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos5420.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 54db8b34b1dc..bddf5496fef2 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -175,6 +175,13 @@
#define CLK_ACLK_G3D 500
#define CLK_G3D 501
#define CLK_SMMU_MIXER 502
+#define CLK_SCLK_UART_ISP 510
+#define CLK_SCLK_SPI0_ISP 511
+#define CLK_SCLK_SPI1_ISP 512
+#define CLK_SCLK_PWM_ISP 513
+#define CLK_SCLK_ISP_SENSOR0 514
+#define CLK_SCLK_ISP_SENSOR1 515
+#define CLK_SCLK_ISP_SENSOR2 516
/* mux clocks */
#define CLK_MOUT_HDMI 640