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authorMichal Simek2013-11-18 16:48:19 +0100
committerMichal Simek2014-02-10 11:21:13 +0100
commitb0504e39c27b00101c9c1fa2c58fd896ae0f64f5 (patch)
tree526bfc125e81fbdb37a8391106070be9f5cfec61 /include/linux/clk
parent5e2182803497c22d50675f0f3af12bf5305e8716 (diff)
ARM: zynq: Map I/O memory on clkc init
The clkc has its registers in the range of the slcr. Instead of passing around the slcr base address pointer, let the clkc get the address from the DT. This prepares the slcr to be a real driver with multiple memory ranges (slcr, clocks, pinctrl,...) Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include/linux/clk')
-rw-r--r--include/linux/clk/zynq.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index e062d317ccce..7a5633b71533 100644
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -22,7 +22,7 @@
#include <linux/spinlock.h>
-void zynq_clock_init(void __iomem *slcr);
+void zynq_clock_init(void);
struct clk *clk_register_zynq_pll(const char *name, const char *parent,
void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,