diff options
| author | Hans Verkuil | 2013-03-08 11:22:03 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab | 2013-03-24 12:02:59 -0300 |
| commit | a0fc58868bbf34d0935947cdf1bc8c0ea32c68c4 (patch) | |
| tree | fd7f5780ea9400cf4f859b846ea9b6a2c81d034b /include/media/saa7115.h | |
| parent | 9ca5470cc1433200698a43de2d6e683815e536e6 (diff) | |
[media] saa7115: add config flag to change the IDQ polarity
Needed by the go7007 driver: it assumes a different polarity of the IDQ
signal, so we need to be able to tell the saa7115 about this.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'include/media/saa7115.h')
| -rw-r--r-- | include/media/saa7115.h | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/include/media/saa7115.h b/include/media/saa7115.h index bab212719591..8b2ecc69a702 100644 --- a/include/media/saa7115.h +++ b/include/media/saa7115.h @@ -21,6 +21,8 @@ #ifndef _SAA7115_H_ #define _SAA7115_H_ +/* s_routing inputs, outputs, and config */ + /* SAA7111/3/4/5 HW inputs */ #define SAA7115_COMPOSITE0 0 #define SAA7115_COMPOSITE1 1 @@ -33,24 +35,33 @@ #define SAA7115_SVIDEO2 8 #define SAA7115_SVIDEO3 9 -/* SAA7115 v4l2_crystal_freq frequency values */ -#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */ -#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ - -/* SAA7115 v4l2_crystal_freq audio clock control flags */ -#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ -#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ -#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ - +/* outputs */ #define SAA7115_IPORT_ON 1 #define SAA7115_IPORT_OFF 0 -/* SAA7111 specific output flags */ +/* SAA7111 specific outputs. */ #define SAA7111_VBI_BYPASS 2 #define SAA7111_FMT_YUV422 0x00 #define SAA7111_FMT_RGB 0x40 #define SAA7111_FMT_CCIR 0x80 #define SAA7111_FMT_YUV411 0xc0 +/* config flags */ +/* Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit + * controls the IDQ signal polarity which is set to 'inverted' if the bit + * it 1 and to 'default' if it is 0. */ +#define SAA7115_IDQ_IS_DEFAULT (1 << 0) + +/* s_crystal_freq values and flags */ + +/* SAA7115 v4l2_crystal_freq frequency values */ +#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */ +#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ + +/* SAA7115 v4l2_crystal_freq audio clock control flags */ +#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ +#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ +#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ + #endif |