diff options
| author | Bjorn Helgaas | 2019-11-12 11:07:36 -0600 |
|---|---|---|
| committer | Bjorn Helgaas | 2019-11-21 07:52:34 -0600 |
| commit | bbdb2f5ecdf1e66b2f09710134db3c2e5c43a958 (patch) | |
| tree | 7d4c16988501fa5fa5aa7ea9d950f9c53c579b9a /include/uapi | |
| parent | b7da3d4df05232d637eff1c0874d20996b98769c (diff) | |
PCI: Add #defines for Enter Compliance, Transmit Margin
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.
Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 29d6e93fd15e..5869e5778a05 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -673,6 +673,8 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |